Commit Graph

391 Commits

Author SHA1 Message Date
Ville Syrjälä 52c4abeec6 drm/i915/psr: Fix PSR sink enable sequence
According to the eDP spec, the source must first configure all
PSR related DPCD registers apart from the actual enable bit,
and only then set the enable bit. Split the current single DPCD
write to two to match the spec.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240911151836.16800-1-ville.syrjala@linux.intel.com
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2024-09-18 23:25:18 +03:00
Jouni Högander 2478e2234d drm/i915/psr: eDP Panel Replay is not supported on pipes other than A and B
Do not allow Panel Replay if pipe is other than A or B.

Bspec: 68920

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2736
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240916085706.2160511-1-jouni.hogander@intel.com
2024-09-18 09:47:14 +03:00
Imre Deak f7c2ed9d4c drm/i915/dp: Fix AUX IO power enabling for eDP PSR
Panel Self Refresh on eDP requires the AUX IO power to be enabled
whenever the output (main link) is enabled. This is required by the
AUX_PHY_WAKE/ML_PHY_LOCK signaling initiated by the HW automatically to
re-enable the main link after it got disabled in power saving states
(see eDP v1.4b, sections 5.1, 6.1.3.3.1.1).

The Panel Replay mode on non-eDP outputs on the other hand is only
supported by keeping the main link active, thus not requiring the above
AUX_PHY_WAKE/ML_PHY_LOCK signaling (eDP v1.4b, section 6.1.3.3.1.2).
Thus enabling the AUX IO power for this case is not required either.

Based on the above enable the AUX IO power only for eDP/PSR outputs.

Bspec: 49274, 53370

v2:
- Add a TODO comment to adjust the requirement for AUX IO based on
  whether the ALPM/main-link off mode gets enabled. (Rodrigo)

Cc: Animesh Manna <animesh.manna@intel.com>
Fixes: b8cf5b5d26 ("drm/i915/panelreplay: Initializaton and compute config for panel replay")
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240910111847.2995725-1-imre.deak@intel.com
2024-09-13 17:42:03 +03:00
Jouni Högander a2d98feb4b drm/i915/psr: Do not wait for PSR being idle on on Panel Replay
We do not have ALPM on DP Panel Replay. Due to this SRD_STATUS[SRD State]
doesn't change from SRDENT_ON after Panel Replay is enabled until it gets
disabled.

On eDP Panel Replay DEEP_SLEEP is not reached.
_psr2_ready_for_pipe_update_locked is waiting DEEP_SLEEP bit getting reset.

Take these into account in Panel Replay code by not waiting PSR getting
idle after enabling VBI.

Fixes: 29fb595d48 ("drm/i915/psr: Panel replay uses SRD_STATUS to track it's status")
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240906070033.289015-5-jouni.hogander@intel.com
2024-09-11 12:53:14 +03:00
Jouni Högander 91463d74b1 drm/i915/psr: Add connector debugfs files for MST connector as well
Connector debugfs files are currently not add for MST connector. We
can now add them as we have taken into account possibility to have
NULL in connector->encoder in intel_attached_dp.

v2: remove TODO comment

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240906070033.289015-4-jouni.hogander@intel.com
2024-09-11 12:52:58 +03:00
Jani Nikula ae19ba915e drm/i915/display: include media/cec-notifier.h and linux/debugfs.h where needed
Use a forward declaration for struct cec_notifier instead of including
media/cec-notifier.h in intel_display_types.h, and only include it where
needed.

Also realize that a lot of places depend on including linux/debugfs.h
via intel_display_types.h -> media/cec-notifier.h -> media/cec.h, and
include that too where needed.

v2: hsw_ips.c also needs debugfs.h (kernel test robot)

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240827104521.4151471-1-jani.nikula@intel.com
2024-09-05 12:21:22 +03:00
Jani Nikula 41a4629621 drm/i915/psr: convert intel_psr.[ch] to struct intel_display
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_psr.[ch] to struct intel_display.

Some stragglers are left behind where needed.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4399b98b07019a8063adbec1043ff7eabb7c1080.1725012870.git.jani.nikula@intel.com
2024-09-03 17:11:00 +03:00
Jani Nikula 5a48d67ac3 drm/i915/display: rename IS_DISPLAY_IP_STEP() to IS_DISPLAY_VER_STEP()
Unify macro naming on VER.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/6861e02f3adf15d56e89890000eb195070c33c9b.1724180287.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-08-22 15:48:03 +03:00
Jouni Högander a8efd8ce28 drm/i915/psr: Prevent Panel Replay if CRC calculation is enabled
Similarly as for PSR2 CRC calculation seems to timeout when Panel Replay is
enabled. Fix this by falling back to PSR if CRC calculation is enabled.

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2266
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240819092549.1298233-1-jouni.hogander@intel.com
2024-08-21 13:55:02 +03:00
Jouni Högander 85582ad0bc drm/i915/psr: Modify dg2_activate_panel_replay to support eDP
There are couple of bits in PSR2_CTL which needs to be written in case of
eDP Panel Replay

Bspec: 68920

v2: use boolean instead of assuming eDP Panel Replay mean Early Transport

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-12-jouni.hogander@intel.com
2024-06-25 08:28:43 +03:00
Jouni Högander 623ad75a01 drm/i915/psr: Check Early Transport for Panel Replay as well
Move Early Transport validity check to be performed for Panel Replay as
well and use Early Transport for eDP Panel Replay always.

v2:set crtc_state->enable_psr2_su_region_et directly (not in if block)

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-11-jouni.hogander@intel.com
2024-06-25 08:28:43 +03:00
Jouni Högander 0cd2bdbf19 drm/i915/psr: Perform scanline indication check for Panel Replay as well
Scanline indication needs to be checked and configure for both PSR2 and
Panel Replay Selective Update. Move this check to
intel_sel_update_config_valid.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-10-jouni.hogander@intel.com
2024-06-25 08:28:43 +03:00
Jouni Högander a18114ebaa drm/i915/psr: Perform psr2 checks related to ALPM for Panel Replay
eDP1.5 support ALPM with Panel Replay as well. We need to check ALPM
related things for Panel Replay as well.

Bspec: 68920

v5:
  - instead of using crtc_state->has_panel_replay provide aux_less flag
v4:
  - do not move _compute_psr2_sdp_prior_scanline_indication
  - move ALPM related checks to separate function
v3: move vblank check as well
v2: do not move Vblank >= PSR2_CTL Block Count Number maximum line count
    check

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-9-jouni.hogander@intel.com
2024-06-25 08:28:43 +03:00
Jouni Högander 0bc96a4ba9 drm/i915/psr: HW will not allow PR on eDP when HDCP enabled
Take into account in Panel Replay compute config that  HW will not allow PR
on eDP when HDCP enabled.

v2: add debug message to print out why Panel Replay is not possible

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-7-jouni.hogander@intel.com
2024-06-25 08:28:43 +03:00
Jouni Högander 397b51ef1a drm/i915/psr: 128b/132b Panel Replay is not supported on eDP
Take into account that 128b/132b Panel Replay is not supported on eDP.

Bspec: 68920

v2:
  - make crtc_state as const
  - add debug message to print out why Panel Replay is not possible

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-6-jouni.hogander@intel.com
2024-06-25 08:28:35 +03:00
Jouni Högander 5d9993f883 drm/i915/psr: Check panel Early Transport capability for eDP PR
Our HW doesn't support panel replay without Early Transport on eDP.

Bspec: 68920

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-5-jouni.hogander@intel.com
2024-06-25 08:25:36 +03:00
Jouni Högander 67cf054737 drm/i915/psr: enable sink for eDP1.5 Panel Replay
eDP1.5 allows Panel Replay on eDP as well. Take this into account when
enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register
accordingly.

v3:
  - set DP_PANEL_REPLAY_CRC_VERIFICATION in PANEL_REPLAY_CONFIG2
  - PANEL_REPLAY_CONFIG2 is available in DP2.1 as well
v2: do not configure ALPM for DP2.0 Panel Replay

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-4-jouni.hogander@intel.com
2024-06-25 08:24:22 +03:00
Jouni Högander dfeb3a249f drm/i915/psr: Inform Panel Replay source support on eDP as well
Display version >= 20 support eDP 1.5. Inform Panel Replay source support
on eDP for display version >= 20.

Bspec: 68920

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-3-jouni.hogander@intel.com
2024-06-25 08:24:10 +03:00
Jouni Högander 897d29ce22 drm/i915/psr: Check panel ALPM capability for eDP Panel Replay
Our HW doesn't support Panel Replay without AUX_LESS ALPM on eDP. Check
panel support for this and prevent eDP panel replay if it doesn't exits.

Bspec: 68920

v3: remove excessive parens
v2: use intel_alpm_aux_less_wake_supported

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-2-jouni.hogander@intel.com
2024-06-25 08:23:27 +03:00
Jouni Högander 582e372f06 drm/i915/psr: Set DP_PSR_SU_REGION_SCANLINE_CAPTURE bit when needed
Setting DP_PSR_SU_REGION_SCANLINE_CAPTURE (Selective Update Region Scan
Line Capture Indication in spec) bit was dropped when psr_enable_sink was
split to _psr_enable_sink and _panel_replay_enable_sink. Add setting it
back.

Fixes: 32f0045f90 ("drm/i915/psr: Split enabling sink for PSR and Panel Replay")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240620103312.903977-1-jouni.hogander@intel.com
2024-06-24 07:31:56 +03:00
Jouni Högander dc9cfe9f1d Revert "drm/i915/psr: Disable early transport by default"
This reverts commit f3c2031db7.

We want to notice possible issues faced with PSR2 Region Early Transport as
early as possible -> let's revert patch disabling Region Early Transport by
default. Also eDP 1.5 Panel Replay requires Early Transport.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-9-jouni.hogander@intel.com
2024-06-19 07:42:11 +03:00
Jouni Högander c52a3187a1 drm/i915/psr: Add new debug bit to disable Panel Replay
Add new debug bit to be used with i915_edp_psr_debug debugfs
interface. This can be used to disable Panel Replay.

v2: ensure that fastset is performed when the bit changes

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-8-jouni.hogander@intel.com
2024-06-19 07:42:10 +03:00
Jouni Högander 3ec391a007 drm/i915/psr: Disable PSR/Panel Replay on sink side for PSR only
Enabling/disabling Panel Replay on sink side has to be done before link
training. We can't disable it in sink side on PSR disable.

Fixes: 88ae6c65ec ("drm/i915/psr: Unify panel replay enable/disable sink")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-7-jouni.hogander@intel.com
2024-06-19 07:42:10 +03:00
Jouni Högander aeb7a0fe21 drm/i915/psr: Disable PSR2 SU Region ET if enable_psr module parameter is set
Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake
if panel supports it despite enable_psr module parameter value. This patch
makes it possible for user to limit used PSR mode and prevent SU Region
Early Transport by setting enable_psr as 2. With default (-1) PSR2 SU
Region Early Transport is allowed.

v2: fix/improve commit desciption

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-6-jouni.hogander@intel.com
2024-06-19 07:42:09 +03:00
Jouni Högander b445130c35 drm/i915/psr: Disable Panel Replay if PSR mode is set via module parameter
If user is specifically limiting PSR mode to PSR1 or PSR2: disable Panel
Replay. With default value -1 all modes are allowed including Panel
Replay. Disabling PSR using value 0 disables Panel Replay as well.

Also own compute config helper is added for Panel Replay. This makes sense
because number of Panel Replay specific checks are increasing.

v2: Squash adding Panel Replay compute config helper

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-5-jouni.hogander@intel.com
2024-06-19 07:42:09 +03:00
Jouni Högander 1eb28818c2 drm/i915/display: Wa 16021440873 is writing wrong register
Wa 16021440873 is writing wrong register. Instead of PIPE_SRCSZ_ERLY_TPT
write CURPOS_ERLY_TPT.

v2: use right offset as well

Fixes: 29cdef8539 ("drm/i915/display: Implement Wa_16021440873")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-3-jouni.hogander@intel.com
2024-06-19 07:42:08 +03:00
Jouni Högander 97db734864 drm/i915/psr: Set SU area width as pipe src width
Currently SU area width is set as MAX_INT. This is causing
problems. Instead set it as pipe src width.

Fixes: 86b26b6aea ("drm/i915/psr: Carry su area in crtc_state")

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-2-jouni.hogander@intel.com
2024-06-19 07:42:07 +03:00
Stanislav Lisovskiy fb4943574f drm/i915: Rename all bigjoiner to joiner
Lets unify both bigjoiner and ultrajoiner under simple "joiner" name,
because in future we might have multiple configurations, involving
multiple bigjoiners, ultrajoiner, however it is possible to use
same api for handling both.

v2: - Renamed back some bigjoiner specific parts for now(Ville)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
[vsyrjala: Catch a few more cases]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607075457.15700-1-stanislav.lisovskiy@intel.com
2024-06-12 22:17:40 +03:00
Jouni Högander ca8a170f73 drm/i915/psr: Wake time is aux less wake time for Panel Replay
When checking vblank length used wake time is aux less wake time for eDP
Panel Replay (vblank length is not checked for DP2.0 Panel Replay).

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-14-jouni.hogander@intel.com
2024-06-11 13:05:14 +03:00
Jouni Högander 99fcf46390 drm/i915/psr: Check vblank against IO buffer wake time on Lunarlake
As Lunarlake doesn't have block count configuration vblank should be
checked against IO buffer wake time.

Bspec: 68920

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-13-jouni.hogander@intel.com
2024-06-11 13:05:05 +03:00
Jouni Högander aeafa46ee3 drm/i915/psr: Take into account SU SDP scanline indication in vblank check
SU SDP scanline indication should be taken into account when checking
vblank length. In Bspec we have:

PSR2_CTL[ SU SDP scanline indication ] = 0: (TRANS_VBLANK Vertical Blank
End- TRANS_VBLANK Vertical Blank Start) > PSR2_CTL Block Count Number value
in lines

PSR2_CTL[ SU SDP scanline indication ] = 1: (TRANS_VBLANK Vertical Blank
End- TRANS_VBLANK Vertical Blank Start- 1) > PSR2_CTL Block Count Number
value in lines

Bspec: 49274

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-12-jouni.hogander@intel.com
2024-06-11 13:04:24 +03:00
Jouni Högander 2e8938a1c5 drm/i915/psr: Move vblank length check to separate function
We are about to add more complexity to vblank length check. It makes sense
to move it to separate function for sake of clarity.

v2: change name to wake_lines_fit_into_vblank

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-11-jouni.hogander@intel.com
2024-06-11 13:03:56 +03:00
Jouni Högander 51ee1f29a9 drm/i915/psr: Print Panel Replay status instead of frame lock status
Currently Panel Replay status printout is printing frame lock status. It
should print Panel Replay status instead. Panel Replay status register
field follows PSR status register field. Use existing PSR code for that.

Fixes: ef75c25e8f ("drm/i915/panelreplay: Debugfs support for panel replay")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-10-jouni.hogander@intel.com
2024-06-11 13:03:36 +03:00
Jouni Högander 672670b5dc drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid
Early Transport is possible and in our HW mandatory on eDP Panel
Replay. Add parameter to intel_psr2_config_et_valid to differentiate
validity check for Panel Replay.

v2: fix intel_dp->psr_dpcd[0] check

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-9-jouni.hogander@intel.com
2024-06-11 13:03:16 +03:00
Jouni Högander 92d03bdee4 drm/i915/alpm: Share alpm support checks with PSR code
Convert intel_alpm_aux_wake_supported and
intel_alpm_aux_less_wake_supported as non-static. Use them in intel_psr.c
instead of local variables.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-8-jouni.hogander@intel.com
2024-06-11 13:02:45 +03:00
Jouni Högander 32f0045f90 drm/i915/psr: Split enabling sink for PSR and Panel Replay
Current intel_psr_enable_sink is a mess due to partly reusing PSR bit
definitions for Panel Replay. Even thought PSR and Panel Replay enable
registers do have common bits they still have also different bits and same
bits with different meaning. For sake of clarity split enabling sink to PSR
and Panel Replay specific parts.

Also fix issue caused by using psr->panel_replay_enabled to early.

Fixes: 88ae6c65ec ("drm/i915/psr: Unify panel replay enable/disable sink")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-7-jouni.hogander@intel.com
2024-06-11 13:02:10 +03:00
Jani Nikula d9abe5f9e5 drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANS
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the MTL_CLKGATE_DIS_TRANS register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b330d86c5e3012513daa36dceffd2db45f0d7850.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07 11:31:23 +03:00
Jouni Högander b330568f0c drm/i915/psr: Add Early Transport into psr debugfs interface
We want to have sink Early Transport capability and usage in our psr
debugfs status interface.

v4: use su_region_et_enabled instead of psr2_su_region_et_valid
v3: remove extra space from "PSR mode:  disabled"
v2: printout "Selective Update enabled (Early Transport)" instead of
    "Selective Update Early Transport enabled"

Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-7-jouni.hogander@intel.com
2024-06-03 11:23:18 +03:00
Jouni Högander 04d0aed082 drm/i915/psr: Allow setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE via debugfs
Currently setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE (0x20) via psr_debug
debugfs interface is not allowed. This patch allows it.

v3:
  - ensure psr is disabled/enabled if enable_psr2_su_region_et changes
  - remove extra space
v2: ensure that fastset is performed when the bit changes

Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-6-jouni.hogander@intel.com
2024-06-03 11:23:09 +03:00
Jouni Högander 0a8c581ce0 drm/i915/psr: Use enable boolean from intel_crtc_state for Early Transport
When enabling Early Transport use
intel_crtc_state->enable_psr2_su_region_et instead of
psr2_su_region_et_valid.

Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Fixes: 467e4e061c ("drm/i915/psr: Enable psr2 early transport as possible")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-4-jouni.hogander@intel.com
2024-06-03 11:22:49 +03:00
Jouni Högander 13d1359d67 drm/i915/psr: Get Early Transport status in intel_psr_pipe_get_config
We are currently not getting Early Transport status information in
intel_psr_pipe_get_config. Fix this.

Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Fixes: 467e4e061c ("drm/i915/psr: Enable psr2 early transport as possible")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-3-jouni.hogander@intel.com
2024-06-03 11:22:38 +03:00
Jouni Högander 0e3771f459 drm/i915/psr: Add Early Transport status boolean into intel_psr
Currently we are purely relying on psr2_su_region_et_valid. Add new boolean
value into intel_psr struct indicating whether Early Transport is enabled
or not and use it instead of psr2_su_region_et_valid for getting Early
Transport status information.

Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-2-jouni.hogander@intel.com
2024-06-03 11:22:04 +03:00
Animesh Manna 5a9b255fdb drm/i915/alpm: Enable lobf from source in ALPM_CTL
Set the Link Off Between Frames Enable bit in ALPM_CTL register.

Note: Lobf need to be enabled adaptive sync fixed refresh mode
where vmin = vmax = flipline, which will arise after cmmr feature
enablement. Will add enabling sequence in a separate patch.

v1: Initial version.
v2: Condition check modified in alpm_configure(). [Jouni]

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-6-animesh.manna@intel.com
2024-05-31 10:55:56 +05:30
Animesh Manna 8bdbde7c4c drm/i915/alpm: Move alpm related code to a new file
Move ALPM feature related code as it will be used for
non-psr panel also thorugh LOBF feature.

v1: Initial version.
v2: Correct ordering in makefile. [Jani]

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-3-animesh.manna@intel.com
2024-05-31 10:47:23 +05:30
Animesh Manna dd73925e3b drm/i915/alpm: Move alpm parameters from intel_psr
ALPM can be enabled for non psr panel and currenly aplm-params are
encapsulated under intel_psr struct, so moving out to intel_dp struct.

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-2-animesh.manna@intel.com
2024-05-31 10:47:22 +05:30
Jouni Högander fec7efe7bf drm/i915/psr: modify psr status debugfs to support eDP Panel Replay
Some PSR2_CTL bits are applicable for eDP panel replay as well.
Dump this register for eDP Panel Replay as well.

Bspec: 68920

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-6-jouni.hogander@intel.com
2024-05-29 08:34:31 +03:00
Jouni Högander f0faeb2e70 drm/i915/psr: Move printing PSR mode to own function
intel_psr_status has grown and is about to grow even. Let's split it a bit
and move printing PSR mode to an own function.

v2: s/intel_psr_psr_mode/intel_psr_print_mode/

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-5-jouni.hogander@intel.com
2024-05-29 08:34:31 +03:00
Jouni Högander 1566b50a43 drm/i915/psr: Move printing sink PSR support to own function
intel_psr_status has grown and is about to grow even. Let's split it a bit
and move printing sink psr support to an own function.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-4-jouni.hogander@intel.com
2024-05-29 08:34:31 +03:00
Jouni Högander 73baf72eb1 drm/i915/psr: Store pr_dpcd in intel_dp
We need pr_dpcd contents for early transport validity check on eDP Panel
Replay and in debugfs interface to dump out panel early transport
capability. Also remove unnecessarily printing out "Panel replay is not
supported by panel"

v2: commit message modified

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-2-jouni.hogander@intel.com
2024-05-29 08:33:14 +03:00
Ville Syrjälä 04c09e4b87 drm/i915: Simplify PIPESRC_ERLY_TPT definition
PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000 range.
so using _MMIO_TRANS2() for it is not really correct. Also since this
is a pipe register, and not present on CHV, the registers will be
equally spaced out, so we can use the simpler _MMIO_PIPE() instead
of _MMIO_PIPE2().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-22 15:45:34 +03:00
Jouni Högander d370a9dba5 drm/i915/psr: PSR2_CTL[Block Count Number] not needed for LunarLake
PSR2_CTL[Block Count Number] is not used by LunarLake do not configure it.

Bspec: 69885

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-4-jouni.hogander@intel.com
2024-05-20 07:34:46 +03:00
Jouni Högander 30dee753ca drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wide
On LunarLake  PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this
into account when enabling PSR2_CTL.

Bspec: 69885

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-3-jouni.hogander@intel.com
2024-05-20 07:34:45 +03:00
Jouni Högander 45430e7b7c drm/i915/psr: LunarLake IO and Fast Wake time line count maximums are 68
On LunarLake maximum for IO and Fast Wake time line counts are 68: 6 bits +
5 lines added by the HW. Take this into account in calculation and when
writing the IO Wake lines.

v2: maximum line count is 68 (6 bits + 5 lines added by HW)

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-2-jouni.hogander@intel.com
2024-05-20 07:34:45 +03:00
Jani Nikula 11abdbc22b drm/i915: pass dev_priv explicitly to CURSURFLIVE
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURSURFLIVE register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/86aa98ad9f883681f5c2e3aba839d02d8591bfbf.1715774156.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-16 11:23:00 +03:00
Ville Syrjälä 8cecf4aec3 drm/i915: Extract intel_cursor_regs.h
Move most cursor register definitions into their own file.
Declutters i915_reg.h a bit more.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-15 14:11:21 +03:00
Jouni Högander 3425b2205d drm/i915/psr: Add panel replay sel update support to debugfs interface
Add panel replay selective update support to debugfs status interface. In
case of sink supporting panel replay we will print out:

Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes

and PSR mode will look like this if printing out enabled panel replay
selective update:

PSR mode: Panel Replay Selective Update Enabled

Current PSR and panel replay printouts remain same.

Cc: Kunal Joshi <kunal1.joshi@intel.com>

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-13-jouni.hogander@intel.com
2024-05-15 10:56:28 +03:00
Jouni Högander c66c670ded drm/i915/psr: Split intel_psr2_config_valid for panel replay
Part of intel_psr2_config_valid is valid for panel replay. rename it as
intel_sel_update_config_valid. Split psr2 specific part and name it as
intel_psr2_config_valid.

v3:
  - move early transport check to psr2 specific check
  - check intel_psr2_config_valid only for non-Panel Replay case
v2:
  - use psr2_global_enabled for panel replay as well
  - goto unsupported instead of return when global enabled check fails

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-12-jouni.hogander@intel.com
2024-05-15 10:56:28 +03:00
Jouni Högander 54599011b7 drm/i915/psr: Do not apply workarounds in case of panel replay
There are some workarounds that are not applicable for panel replay. Do not
apply these if panel replay is used.

Bspec: 66624, 50422

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-10-jouni.hogander@intel.com
2024-05-15 10:56:28 +03:00
Jouni Högander 29fb595d48 drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
DP Panel replay uses SRD_STATUS to track it's status despite selective
update mode.

Bspec: 53370, 68920

v4:
  - use PSR2_STATUS for eDP Panel Replay
  - handle intel_psr_wait_exit_locked as well
v3:
  - do not use PSR2_STATUS for PSR1
v2:
  - use intel_dp_is_edp to differentiate
  - modify debugfs status as well

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-9-jouni.hogander@intel.com
2024-05-15 10:56:27 +03:00
Jouni Högander d210d8c0df drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
Currently intel_dp_get_su_granularity doesn't support panel replay.
This fix modifies it to support panel replay as well.

v4:
  - use drm_dp_dpcd_readb instead of drm_dp_dpcd_read
  - ensure return value is 0 if drm_dp_dpcd_readb fails
v3: use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY
v2: rely on PSR definitions on common bits

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-8-jouni.hogander@intel.com
2024-05-15 10:56:27 +03:00
Jouni Högander 3a745dfc71 drm/i915/psr: Detect panel replay selective update support
Add new boolean to store panel replay selective update support of sink into
intel_psr struct.  Detect panel replay selective update support and store
it into this new boolean.

v3: Clear sink_panel_replay_su_support in intel_dp_detect
v2: Merge adding new boolean into this patch

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-7-jouni.hogander@intel.com
2024-05-15 10:56:27 +03:00
Jouni Högander ba7cf33f23 drm/i915/psr: Rename psr2_enabled as sel_update_enabled
We are about to reuse psr2_enabled for panel replay as well. Rename
it as sel_update_enabled to avoid confusion.

v3: Rebase
v2: Rebase

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-5-jouni.hogander@intel.com
2024-05-15 10:54:53 +03:00
Jouni Högander 1e52db8a43 drm/i915/psr: Rename has_psr2 as has_sel_update
We are going to reuse has_psr2 for panel_replay as well. Rename it
as has_sel_update to avoid confusion.

v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp
v2: Rebase

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-2-jouni.hogander@intel.com
2024-05-15 10:54:51 +03:00
Jani Nikula accd3e041e drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTL
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PORT_ALPM_LFPS_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f8a3bbade94258852b8129c5f5918fb06ceab54b.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 11:24:53 +03:00
Jani Nikula 7f4eae0a94 drm/i915: pass dev_priv explicitly to PORT_ALPM_CTL
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PORT_ALPM_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/86e8f5649c822ff6fa0502ad88964bfcb269c6c5.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 11:24:53 +03:00
Jani Nikula 13b77ac5dc drm/i915: pass dev_priv explicitly to ALPM_CTL
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the ALPM_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/96da9be36dc93fa9a7c329f25ff963e4998998c1.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:41 +03:00
Jani Nikula db92d423dc drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPT
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_SRCSZ_ERLY_TPT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b37217f55702fc10190c2c5aded7d845a36766f6.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:39 +03:00
Jani Nikula dd17285e94 drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTL
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR2_MAN_TRK_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/72934c8ac3a923ca0c12fc6cdeec1e0b87ecc4a4.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:38 +03:00
Jani Nikula a0d1cfa86c drm/i915: pass dev_priv explicitly to PSR2_SU_STATUS
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR2_SU_STATUS register macro.

v2: Expand from _PSR2_SU_STATUS to PSR2_SU_STATUS (Rodrigo)

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240502103925.1829104-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:35 +03:00
Jani Nikula d82d1a6be6 drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUS
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR2_STATUS register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/5d86a48f51ae6fa4c5a3abf098440a94d07de870.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:34 +03:00
Jani Nikula ccd5bc537b drm/i915: pass dev_priv explicitly to PSR_EVENT
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR_EVENT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/9bc5819afa46416eb8f12ac050ed4d3bcde34b63.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:32 +03:00
Jani Nikula 9b0dddd50e drm/i915: pass dev_priv explicitly to EDP_PSR2_CTL
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR2_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e7df99445716ce404bbfe733dd962288a529cf0d.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:31 +03:00
Jani Nikula 83f4ccb3f3 drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUG
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_DEBUG register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/187dd49632d46e67705bd258ed7f9eabdeb108b2.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:30 +03:00
Jani Nikula 5aa0cb6b1e drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNT
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_PERF_CNT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/21805960967ab88c1418037b98fe3e051eb00608.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:29 +03:00
Jani Nikula 218f3d28d1 drm/i915: pass dev_priv explicitly to EDP_PSR_STATUS
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_STATUS register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4aaa0187b16d2b96b5b4b1d775d7349c9fc28c7c.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:27 +03:00
Jani Nikula 4c3cbdb12d drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATA
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_AUX_DATA register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4e3dc15b170c2b64168e46ebf1802d63df34b4a2.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:26 +03:00
Jani Nikula cf3d5f89a6 drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTL
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_AUX_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/66ec1f81be49c87cd9613ba052ce6fd50362d0e0.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:25 +03:00
Jani Nikula 7a7a4c4eeb drm/i915: pass dev_priv explicitly to TRANS_PSR_IIR
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_PSR_IIR register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3a03109d11e7f55a456c3e5ef28d3ffa69582d3d.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:23 +03:00
Jani Nikula f9f8f84717 drm/i915: pass dev_priv explicitly to TRANS_PSR_IMR
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_PSR_IMR register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/09e9c11ffb669dac901c2416462a8f3dabc86020.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:22 +03:00
Jani Nikula 676a6a1c99 drm/i915: pass dev_priv explicitly to EDP_PSR_CTL
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/198858bc3925c02c0975670e3ebb5ce2084ac658.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:20 +03:00
Jani Nikula 1d231cd898 drm/i915: pass dev_priv explicitly to TRANS_EXITLINE
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_EXITLINE register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/eb1e5fe155daf2d271af76e683a1f3f33e34403a.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06 10:25:19 +03:00
Jouni Högander 3a487d111d drm/i915/psr: Use crtc_state->port_clock instead of intel_dp->link_rate
Intel_dp->link_rate is not yet set at this point. Instead use
crtc_state->port_clock.

Fixes: 0dd21f8369 ("drm/i915/psr: Silence period and lfps half cycle")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240409085759.178235-1-jouni.hogander@intel.com
2024-04-11 12:09:48 +03:00
Ville Syrjälä 372fa0c79d drm/i915/psr: Disable PSR when bigjoiner is used
Bigjoiner seem to be causing all kinds of grief to the PSR
code currently. I don't believe there is any hardware issue
but the code simply not handling this correctly. For now
just disable PSR when bigjoiner is needed.

Cc: stable@vger.kernel.org
Link: https://patchwork.freedesktop.org/patch/msgid/20240404213441.17637-3-ville.syrjala@linux.intel.com
Reviewed-by: Arun R Murthy <arun.r.mruthy@intel.com>
Acked-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2024-04-08 15:27:24 +03:00
Jouni Högander ac9ef32732 drm/i915/psr: Panel replay has to be enabled before link training
Panel replay has to be enabled on sink side before link training. Take this
into account in fastset check and in initial fastset check.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-9-jouni.hogander@intel.com
2024-04-08 10:28:55 +03:00
Jouni Högander 88ae6c65ec drm/i915/psr: Unify panel replay enable/disable sink
Unify enabling and disabling of psr/panel replay for a sink. Modify
intel_psr_enable_sink accordingly and use it for both cases.

v3:
  - move psr2_su_region_et_valid to be check for PSR2 only
v2:
  - enable panel replay for sink before link training
  - write ALPM_CONFIG only for PSR
  - add DP_PSR_CRC_VERIFICATION only for PSR
  - take care of disable sink as well

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-8-jouni.hogander@intel.com
2024-04-08 10:28:54 +03:00
Jouni Högander 251ff160c4 drm/i915/psr: Do not write registers/bits not applicable for panel replay
Bspec is saying this
mask register: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug]
are used in panel replay mode.

Status register: Only SRD_STATUS[SRD state] field is used in panel replay
mode.

Due to this stop writing and reading registers and bits not used by panel
replay if panel replay is used.

Bspec: 53370, 68920

v2:
  - use intel_dp_is_edp with PSR_MASK register
  - handle LunarLake as well
  - hanle ALPM configuration as well

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-7-jouni.hogander@intel.com
2024-04-08 10:28:54 +03:00
Jouni Högander b7fc3d12a1 drm/i915/psr: Check possible errors for panel replay as well
On HPD interrupt we want to check if the reason for HPD was some panel
replay error detected by monitor/panel. This is already done for PSR. We
want to do this for panel replay as well. Modify intel_psr_short_pulse to
support panel replay as well.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-6-jouni.hogander@intel.com
2024-04-08 10:28:53 +03:00
Jouni Högander 5d1e4cfa9c drm/i915/psr: Do not update phy power state in case of non-eDP panel replay
Currently panel replay is supporting only main link on mode -> Do not
update phy power state for non-eDP panel replay.

Bspec: 53370

v2: use intel_dp_is_edp to differentiate

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-5-jouni.hogander@intel.com
2024-04-08 10:28:53 +03:00
Jouni Högander 72c222838d drm/i915/psr: Intel_psr_pause/resume needs to support panel replay
Currently intel_psr_pause and intel_psr_resume do nothing in case of panel
replay. Change them to perform pause and return also in case of panel
replay.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-4-jouni.hogander@intel.com
2024-04-08 10:28:52 +03:00
Jouni Högander 5afa6e4960 drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well
Current code is setting only intel_crtc_state->has_panel_replay in panel
replay case. There are lots of stuff behind intel_crtc_state->has_psr that
is needed for panel replay as well. Instead of converting each check to
has_psr || has_panel_replay set has_psr in case of panel replay as
well. Code can then differentiate between psr and panel replay by using
intel_crtc_state->has_panel_replay.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-3-jouni.hogander@intel.com
2024-04-08 10:28:52 +03:00
Jouni Högander 7de3363e60 drm/i915/psr: Add some documentation of variables used in psr code
We are adding more boolean variable into intel_psr and intel_crtc_state
structs. Add some documentation about these for sake of clarity.

v2: Modify has_psr +  has_panel_replay to mean panel replay

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-2-jouni.hogander@intel.com
2024-04-08 10:28:51 +03:00
Jouni Högander 71cdfa8cad drm/i915/psr: Do not write ALPM configuration for PSR1 or DP2.0 Panel Replay
No need to write ALPM configuration for DP2.0 Panel Replay or PSR1.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240328141928.1311284-6-jouni.hogander@intel.com
2024-04-02 12:15:43 +03:00
Jouni Högander 1ccbf13586 drm/i915/psr: Enable ALPM on source side for eDP Panel replay
Enable ALPM AUX-Less on source side for Panel Replay eDP. Also write all
calculated AUX-Less configuration values accordingly. Enabling it on sink
side is in upcoming patch.

Bspec: 71477

v5:
  - mention enable is only on source side in commit message
v4:
  - add comment explaining why AUX less is enabled on eDP panel replay
    without any extra checks
v3:
  - do not use alpm_ctl as uninitialized variable
v2:
  - do not set AUX-Wake related bits for AUX-Less case
  - drop switch to active latency
  - add SLEEP_HOLD_TIME_50_SYMBOLS
  - add PORT_ALPM_CTL_MAX_PHY_SWING_HOLD

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240328141928.1311284-5-jouni.hogander@intel.com
2024-04-02 12:15:43 +03:00
Jouni Högander 0dd21f8369 drm/i915/psr: Silence period and lfps half cycle
Add get function for silence period and lfps half cycle. Values are taken
from the tables in bspec.

Bspec: 71632

v3:
  - use PORT_ALPM_CTL_SILENCE_PERIOD_MASK instead of value 255
  - use PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK instead of
    value 31
v2:
  - fix some checks
  - add some more comments

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240328141928.1311284-4-jouni.hogander@intel.com
2024-04-02 12:15:43 +03:00
Jouni Högander da6a9836ac drm/i915/psr: Calculate aux less wake time
Calculate aux less wake time and store it into alpm_params struct

Bspec: 71477

v4:
  - re-use fast_wake_lines to store aux_less_wake_lines
v3:
  - use ALPM_CTL_AUX_LESS_WAKE_TIME_MASK instead of value 63
v2:
  - use variables instead of values directly
  - fix max value
  - move converting port clock to Mhz into _lnl_compute_aux_less_wake_time

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240328141928.1311284-3-jouni.hogander@intel.com
2024-04-02 12:15:43 +03:00
Jouni Högander 29cdef8539 drm/i915/display: Implement Wa_16021440873
This patch is implementing Wa_16021440873.

Bspec: 74151

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240319123327.1661097-6-jouni.hogander@intel.com
2024-03-28 15:16:04 +02:00
Jouni Högander d37b3dac68 drm/i915/psr: Fix intel_psr2_sel_fetch_et_alignment usage
Currently we are not aligning selective update area to cover cursor fully
when cursor is not updated by itself but still in the selective update
area. Fix this by checking cursor separately after
drm_atomic_add_affected_planes.

Bspec: 68927

Fixes: 1bff93b8bc ("drm/i915/psr: Extend SU area to cover cursor fully if needed")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240319123327.1661097-4-jouni.hogander@intel.com
2024-03-28 15:15:35 +02:00
Jouni Högander b52c4093b0 drm/i915/psr: Move writing early transport pipe src
Currently PIPE_SRCSZ_ERLY_TPT is written in
intel_display.c:intel_set_pipe_src_size. This doesn't work as
intel_set_pipe_src_size is called only on modeset.

Bspec: 68927

Fixes: 3291bbb93e ("drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transport")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240319123327.1661097-3-jouni.hogander@intel.com
2024-03-28 15:04:41 +02:00
Jouni Högander f3b899f0b4 drm/i915/psr: Calculate PIPE_SRCSZ_ERLY_TPT value
When early transport is enabled we need to write PIPE_SRCSZ_ERLY_TPT on
every flip doing selective update. This patch calculates
PIPE_SRCSZ_ERLY_TPT same way as is done for PSR2_MAN_TRK_CTL value and
stores i in intel_crtc_state->pipe_srcsz_early_tpt to be written later
during flip.

Bspec: 68927

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240319123327.1661097-2-jouni.hogander@intel.com
2024-03-28 15:04:41 +02:00
Jani Nikula 0a099232d2 drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state()
Pass encoder to intel_snps_phy_update_psr_power_state(). The encoder
will be more helpful than just port in the subsequent changes.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4711919a9834cf4a49fd665009ba9d44b4b42bc4.1710949619.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-03-21 14:10:11 +02:00