Bing Guo 1fc31638eb drm/amd/display: Fix bpc calculation for specific encodings ... [Why] 1. YCbCr 4:2:2 8bpc/10bpc modes are blocked for HDMI by policy 2. A YCbCr 4:2:0 calculation error blocked some 4:2:0 timing modes [How] YCbCr 4:2:2 8bpc/10bpc modes are allowed for HDMI Fix YCbCr 4:2:0 calculation error Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Bing Guo <Bing.Guo@amd.com> Reviewed-by: Chris Park <chris.park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-11-03 12:32:34 -04:00
..
dcn20	drm/amd/display: Re-arrange FPU code structure for dcn2x	2021-10-06 15:49:24 -04:00
dcn21	…
dcn30	drm/amd/display: Fix bpc calculation for specific encodings	2021-11-03 12:32:34 -04:00
dcn31	drm/amd/display: Fix bpc calculation for specific encodings	2021-11-03 12:32:34 -04:00
dcn301	drm/amd/display: move FPU associated DCN301 code to DML folder	2021-10-28 14:26:50 -04:00
dsc	drm/amd/display: move FPU associated DSC code to DML folder	2021-10-28 14:26:14 -04:00
Makefile	drm/amd/display: move FPU associated DCN301 code to DML folder	2021-10-28 14:26:50 -04:00
dc_features.h	…
display_mode_enums.h	…
display_mode_lib.c	…
display_mode_lib.h	…
display_mode_structs.h	…
display_mode_vba.c	…
display_mode_vba.h	…
display_rq_dlg_helpers.c	…
display_rq_dlg_helpers.h	…
dml1_display_rq_dlg_calc.c	…
dml1_display_rq_dlg_calc.h	…
dml_inline_defs.h	…
dml_logger.h	…