mirror of https://github.com/torvalds/linux.git
145 lines
3.7 KiB
C
145 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/arm-smccc.h>
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/slab.h>
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#define AIROHA_SIP_AVS_HANDLE 0x82000301
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#define AIROHA_AVS_OP_BASE 0xddddddd0
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#define AIROHA_AVS_OP_MASK GENMASK(1, 0)
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#define AIROHA_AVS_OP_FREQ_DYN_ADJ (AIROHA_AVS_OP_BASE | \
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FIELD_PREP(AIROHA_AVS_OP_MASK, 0x1))
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#define AIROHA_AVS_OP_GET_FREQ (AIROHA_AVS_OP_BASE | \
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FIELD_PREP(AIROHA_AVS_OP_MASK, 0x2))
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struct airoha_cpu_pmdomain_priv {
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struct clk_hw hw;
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struct generic_pm_domain pd;
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};
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static long airoha_cpu_pmdomain_clk_round(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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return rate;
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}
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static unsigned long airoha_cpu_pmdomain_clk_get(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct arm_smccc_res res;
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arm_smccc_1_1_invoke(AIROHA_SIP_AVS_HANDLE, AIROHA_AVS_OP_GET_FREQ,
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0, 0, 0, 0, 0, 0, &res);
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/* SMCCC returns freq in MHz */
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return (int)(res.a0 * 1000 * 1000);
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}
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/* Airoha CPU clk SMCC is always enabled */
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static int airoha_cpu_pmdomain_clk_is_enabled(struct clk_hw *hw)
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{
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return true;
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}
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static const struct clk_ops airoha_cpu_pmdomain_clk_ops = {
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.recalc_rate = airoha_cpu_pmdomain_clk_get,
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.is_enabled = airoha_cpu_pmdomain_clk_is_enabled,
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.round_rate = airoha_cpu_pmdomain_clk_round,
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};
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static int airoha_cpu_pmdomain_set_performance_state(struct generic_pm_domain *domain,
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unsigned int state)
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{
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struct arm_smccc_res res;
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arm_smccc_1_1_invoke(AIROHA_SIP_AVS_HANDLE, AIROHA_AVS_OP_FREQ_DYN_ADJ,
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0, state, 0, 0, 0, 0, &res);
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/* SMC signal correct apply by unsetting BIT 0 */
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return res.a0 & BIT(0) ? -EINVAL : 0;
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}
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static int airoha_cpu_pmdomain_probe(struct platform_device *pdev)
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{
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struct airoha_cpu_pmdomain_priv *priv;
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struct device *dev = &pdev->dev;
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const struct clk_init_data init = {
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.name = "cpu",
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.ops = &airoha_cpu_pmdomain_clk_ops,
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/* Clock with no set_rate, can't cache */
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.flags = CLK_GET_RATE_NOCACHE,
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};
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struct generic_pm_domain *pd;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/* Init and register a get-only clk for Cpufreq */
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priv->hw.init = &init;
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ret = devm_clk_hw_register(dev, &priv->hw);
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if (ret)
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return ret;
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
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&priv->hw);
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if (ret)
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return ret;
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/* Init and register a PD for CPU */
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pd = &priv->pd;
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pd->name = "cpu_pd";
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pd->flags = GENPD_FLAG_ALWAYS_ON;
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pd->set_performance_state = airoha_cpu_pmdomain_set_performance_state;
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ret = pm_genpd_init(pd, NULL, false);
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if (ret)
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return ret;
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ret = of_genpd_add_provider_simple(dev->of_node, pd);
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if (ret)
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goto err_add_provider;
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platform_set_drvdata(pdev, priv);
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return 0;
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err_add_provider:
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pm_genpd_remove(pd);
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return ret;
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}
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static void airoha_cpu_pmdomain_remove(struct platform_device *pdev)
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{
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struct airoha_cpu_pmdomain_priv *priv = platform_get_drvdata(pdev);
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of_genpd_del_provider(pdev->dev.of_node);
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pm_genpd_remove(&priv->pd);
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}
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static const struct of_device_id airoha_cpu_pmdomain_of_match[] = {
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{ .compatible = "airoha,en7581-cpufreq" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, airoha_cpu_pmdomain_of_match);
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static struct platform_driver airoha_cpu_pmdomain_driver = {
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.probe = airoha_cpu_pmdomain_probe,
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.remove = airoha_cpu_pmdomain_remove,
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.driver = {
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.name = "airoha-cpu-pmdomain",
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.of_match_table = airoha_cpu_pmdomain_of_match,
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},
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};
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module_platform_driver(airoha_cpu_pmdomain_driver);
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MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
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MODULE_DESCRIPTION("CPU PM domain driver for Airoha SoCs");
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MODULE_LICENSE("GPL");
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