Swapnil Jakhade 351e07e6b2 phy: cadence-torrent: Add PCIe multilink + USB with same SSC register config for 100 MHz refclk ... Add register sequences and support for PCIe multilink + USB configuration for 100MHz reference clock. The same SSC is used for both PCIe and USB. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Co-developed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20250616064705.3225758-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2025-06-16 22:37:19 +05:30
..
Kconfig	phy: cadence: Add Cadence D-PHY Rx driver	2022-03-02 19:54:42 +05:30
Makefile	phy: cadence: Add Cadence D-PHY Rx driver	2022-03-02 19:54:42 +05:30
cdns-dphy-rx.c	phy: Explicitly include correct DT includes	2023-07-17 11:52:56 +05:30
cdns-dphy.c	phy: Switch back to struct platform_driver::remove()	2024-10-17 20:33:03 +05:30
phy-cadence-salvo.c	phy: cadence: salvo: Add cdns,usb2-disconnect-threshold-microvolt property	2023-05-19 23:14:06 +05:30
phy-cadence-sierra.c	phy: cadence: Sierra: Add PCIe + USB PHY multilink configuration	2025-06-15 19:49:33 +05:30
phy-cadence-torrent.c	phy: cadence-torrent: Add PCIe multilink + USB with same SSC register config for 100 MHz refclk	2025-06-16 22:37:19 +05:30