mirror of https://github.com/torvalds/linux.git
120 lines
3.8 KiB
Rust
120 lines
3.8 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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use core::marker::PhantomData;
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use kernel::device;
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use kernel::prelude::*;
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use kernel::time::Delta;
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use crate::driver::Bar0;
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use crate::falcon::{
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Falcon, FalconBromParams, FalconEngine, FalconModSelAlgo, PeregrineCoreSelect,
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};
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use crate::regs;
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use crate::util;
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use super::FalconHal;
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fn select_core_ga102<E: FalconEngine>(bar: &Bar0) -> Result {
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let bcr_ctrl = regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE);
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if bcr_ctrl.core_select() != PeregrineCoreSelect::Falcon {
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regs::NV_PRISCV_RISCV_BCR_CTRL::default()
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.set_core_select(PeregrineCoreSelect::Falcon)
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.write(bar, E::BASE);
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// TIMEOUT: falcon core should take less than 10ms to report being enabled.
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util::wait_on(Delta::from_millis(10), || {
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let r = regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE);
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if r.valid() {
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Some(())
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} else {
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None
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}
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})?;
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}
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Ok(())
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}
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fn signature_reg_fuse_version_ga102(
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dev: &device::Device,
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bar: &Bar0,
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engine_id_mask: u16,
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ucode_id: u8,
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) -> Result<u32> {
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// TODO[REGA]: The ucode fuse versions are contained in the
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// FUSE_OPT_FPF_<ENGINE>_UCODE<X>_VERSION registers, which are an array. Our register
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// definition macros do not allow us to manage them properly, so we need to hardcode their
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// addresses for now. Clean this up once we support register arrays.
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// Each engine has 16 ucode version registers numbered from 1 to 16.
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if ucode_id == 0 || ucode_id > 16 {
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dev_err!(dev, "invalid ucode id {:#x}", ucode_id);
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return Err(EINVAL);
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}
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// Base address of the FUSE registers array corresponding to the engine.
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let reg_fuse_base = if engine_id_mask & 0x0001 != 0 {
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regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::OFFSET
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} else if engine_id_mask & 0x0004 != 0 {
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regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::OFFSET
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} else if engine_id_mask & 0x0400 != 0 {
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regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::OFFSET
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} else {
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dev_err!(dev, "unexpected engine_id_mask {:#x}", engine_id_mask);
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return Err(EINVAL);
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};
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// Read `reg_fuse_base[ucode_id - 1]`.
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let reg_fuse_version =
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bar.read32(reg_fuse_base + ((ucode_id - 1) as usize * core::mem::size_of::<u32>()));
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// TODO[NUMM]: replace with `last_set_bit` once it lands.
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Ok(u32::BITS - reg_fuse_version.leading_zeros())
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}
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fn program_brom_ga102<E: FalconEngine>(bar: &Bar0, params: &FalconBromParams) -> Result {
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regs::NV_PFALCON2_FALCON_BROM_PARAADDR::default()
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.set_value(params.pkc_data_offset)
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.write(bar, E::BASE);
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regs::NV_PFALCON2_FALCON_BROM_ENGIDMASK::default()
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.set_value(u32::from(params.engine_id_mask))
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.write(bar, E::BASE);
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regs::NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID::default()
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.set_ucode_id(params.ucode_id)
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.write(bar, E::BASE);
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regs::NV_PFALCON2_FALCON_MOD_SEL::default()
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.set_algo(FalconModSelAlgo::Rsa3k)
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.write(bar, E::BASE);
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Ok(())
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}
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pub(super) struct Ga102<E: FalconEngine>(PhantomData<E>);
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impl<E: FalconEngine> Ga102<E> {
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pub(super) fn new() -> Self {
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Self(PhantomData)
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}
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}
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impl<E: FalconEngine> FalconHal<E> for Ga102<E> {
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fn select_core(&self, _falcon: &Falcon<E>, bar: &Bar0) -> Result {
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select_core_ga102::<E>(bar)
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}
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fn signature_reg_fuse_version(
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&self,
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falcon: &Falcon<E>,
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bar: &Bar0,
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engine_id_mask: u16,
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ucode_id: u8,
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) -> Result<u32> {
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signature_reg_fuse_version_ga102(&falcon.dev, bar, engine_id_mask, ucode_id)
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}
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fn program_brom(&self, _falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams) -> Result {
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program_brom_ga102::<E>(bar, params)
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}
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}
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