Ovidiu Bunea 70f0b051f8 drm/amd/display: Correct sequences and delays for DCN35 PG & RCG ... [why] The current PG & RCG programming in driver has some gaps and incorrect sequences. [how] Added delays after ungating clocks to allow ramp up, increased polling to allow more time for power up, and removed the incorrect sequences. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 1bde5584e2) Cc: stable@vger.kernel.org		2025-09-09 12:25:22 -04:00
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hw	drm/amd/display: Correct sequences and delays for DCN35 PG & RCG	2025-09-09 12:25:22 -04:00
bw_fixed.h	…
clock_source.h	drm/amd/display: Refactor input mode programming for DIG FIFO	2024-05-08 14:57:04 -04:00
compressor.h	…
core_status.h	drm/amd/display: Add new DP tunnel bandwidth validation	2025-06-24 09:55:35 -04:00
core_types.h	drm/amd/display: MPC basic allocation logic and TMZ	2025-07-15 14:07:51 -04:00
custom_float.h	…
dce_calcs.h	…
dcn_calc_math.h	…
dcn_calcs.h	drm/amd/display: replace fast_validate with enum dc_validate_mode	2025-06-03 15:36:23 -04:00
link.h	drm/amd/display: Remove unused tunnel BW validation	2025-06-30 11:58:36 -04:00
link_enc_cfg.h	drm/amd/display: Remove unused link_enc_cfg_get_link_enc_used_by_stream	2025-02-12 21:03:03 -05:00
link_hwss.h	…
reg_helper.h	drm/amd/display: Use sync version of indirect register access.	2025-04-07 15:18:31 -04:00
resource.h	drm/amd/display: Move mcache allocation programming from DML to resource	2025-05-16 13:38:36 -04:00
vm_helper.h	…