Dillon Varone 3556dac828 drm/amd/display: Fix divide by zero when calculating min ODM factor ... [WHY&HOW] If the debug option is set to disable_dsc the max slice width and/or dispclk can be zero. This causes a divide by zero when calculating the min ODM combine factor. Add a check to ensure they are valid first. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2025-07-28 16:24:05 -04:00
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dcn20	drm/amd/display: Refactoring DSC enum dsc_bits_per_comp.	2025-05-05 12:54:18 -04:00
dcn35	drm/amd/display: Reset DSC memory status	2024-06-27 17:10:37 -04:00
dcn401	drm/amd/display: Refactor DSC cap calculations	2025-07-15 14:07:51 -04:00
Makefile	drm/amd/display: Fix POWERPC_64 compilation	2024-05-20 16:20:25 -04:00
dc_dsc.c	drm/amd/display: Fix divide by zero when calculating min ODM factor	2025-07-28 16:24:05 -04:00
dsc.h	drm/amd/display: Make dcn401_initialize_min_clocks() available to other compilation units	2025-07-15 14:07:51 -04:00
dscc_types.h	drm/amd/display: add rc_params_override option in dc_dsc_config	2023-01-31 14:00:51 -05:00
rc_calc.c	drm/amd/display: Rename DCN config to FP	2023-03-07 14:22:40 -05:00
rc_calc.h	drm/amd/display: fixed an error related to 4:2:0/4:2:2 DSC	2021-11-24 14:06:52 -05:00
rc_calc_dpi.c	drm/amd/display: Update DSC compute parameter calculation	2024-04-09 22:05:58 -04:00