mirror of https://github.com/torvalds/linux.git
f53d0f48a8
[Why] For some pixel clock margin sensitive external monitor, we could not keep original DP ref clock for the ASICs supported SSC DP ref clock. [How] From slicon design team's comment, we have to apply the adjusted DP ref clock for DP devices. DP 128b (DP2) signals uses the DTBCLK not DP ref. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Yiling Chen <yi-ling.chen2@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Mark Broadworth <mark.broadworth@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
||
|---|---|---|
| .. | ||
| Makefile | ||
| dce_abm.c | ||
| dce_abm.h | ||
| dce_audio.c | ||
| dce_audio.h | ||
| dce_aux.c | ||
| dce_aux.h | ||
| dce_clk_mgr.c | ||
| dce_clock_source.c | ||
| dce_clock_source.h | ||
| dce_dmcu.c | ||
| dce_dmcu.h | ||
| dce_i2c.c | ||
| dce_i2c.h | ||
| dce_i2c_hw.c | ||
| dce_i2c_hw.h | ||
| dce_i2c_sw.c | ||
| dce_i2c_sw.h | ||
| dce_ipp.c | ||
| dce_ipp.h | ||
| dce_link_encoder.c | ||
| dce_link_encoder.h | ||
| dce_mem_input.c | ||
| dce_mem_input.h | ||
| dce_opp.c | ||
| dce_opp.h | ||
| dce_panel_cntl.c | ||
| dce_panel_cntl.h | ||
| dce_scl_filters.c | ||
| dce_scl_filters_old.c | ||
| dce_stream_encoder.c | ||
| dce_stream_encoder.h | ||
| dce_transform.c | ||
| dce_transform.h | ||
| dmub_abm.c | ||
| dmub_abm.h | ||
| dmub_abm_lcd.c | ||
| dmub_abm_lcd.h | ||
| dmub_hw_lock_mgr.c | ||
| dmub_hw_lock_mgr.h | ||
| dmub_outbox.c | ||
| dmub_outbox.h | ||
| dmub_psr.c | ||
| dmub_psr.h | ||
| dmub_replay.c | ||
| dmub_replay.h | ||