Paul Hsieh 8747075f54 drm/amd/display: read invalid ddc pin status cause engine busy ... [Why] There is no DDC_6 pin on new asic cause the mapping table is incorrect. When app try to access DDC_VGA port, driver read an invalid ddc pin status and report engine busy. [How] Add dummy DDC_6 pin to align gpio structure. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-12-06 10:16:24 -05:00
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hw_factory_dcn32.c	drm/amd/display: read invalid ddc pin status cause engine busy	2022-12-06 10:16:24 -05:00
hw_factory_dcn32.h	…
hw_translate_dcn32.c	…
hw_translate_dcn32.h	…