mirror of https://github.com/torvalds/linux.git
463 lines
15 KiB
C
463 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2025 Arm Ltd.
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#ifndef MPAM_INTERNAL_H
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#define MPAM_INTERNAL_H
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#include <linux/arm_mpam.h>
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#include <linux/cpumask.h>
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#include <linux/io.h>
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#include <linux/llist.h>
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#include <linux/mutex.h>
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#include <linux/srcu.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define MPAM_MSC_MAX_NUM_RIS 16
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struct platform_device;
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/*
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* Structures protected by SRCU may not be freed for a surprising amount of
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* time (especially if perf is running). To ensure the MPAM error interrupt can
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* tear down all the structures, build a list of objects that can be garbage
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* collected once synchronize_srcu() has returned.
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* If pdev is non-NULL, use devm_kfree().
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*/
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struct mpam_garbage {
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/* member of mpam_garbage */
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struct llist_node llist;
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void *to_free;
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struct platform_device *pdev;
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};
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struct mpam_msc {
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/* member of mpam_all_msc */
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struct list_head all_msc_list;
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int id;
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struct platform_device *pdev;
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/* Not modified after mpam_is_enabled() becomes true */
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enum mpam_msc_iface iface;
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u32 nrdy_usec;
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cpumask_t accessibility;
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/*
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* probe_lock is only taken during discovery. After discovery these
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* properties become read-only and the lists are protected by SRCU.
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*/
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struct mutex probe_lock;
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bool probed;
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u16 partid_max;
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u8 pmg_max;
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unsigned long ris_idxs;
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u32 ris_max;
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/* mpam_msc_ris of this component */
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struct list_head ris;
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/*
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* part_sel_lock protects access to the MSC hardware registers that are
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* affected by MPAMCFG_PART_SEL. (including the ID registers that vary
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* by RIS).
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* If needed, take msc->probe_lock first.
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*/
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struct mutex part_sel_lock;
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/*
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* mon_sel_lock protects access to the MSC hardware registers that are
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* affected by MPAMCFG_MON_SEL, and the mbwu_state.
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* Access to mon_sel is needed from both process and interrupt contexts,
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* but is complicated by firmware-backed platforms that can't make any
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* access unless they can sleep.
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* Always use the mpam_mon_sel_lock() helpers.
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* Accesses to mon_sel need to be able to fail if they occur in the wrong
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* context.
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* If needed, take msc->probe_lock first.
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*/
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raw_spinlock_t _mon_sel_lock;
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unsigned long _mon_sel_flags;
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void __iomem *mapped_hwpage;
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size_t mapped_hwpage_sz;
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struct mpam_garbage garbage;
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};
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/* Returning false here means accesses to mon_sel must fail and report an error. */
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static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc)
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{
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/* Locking will require updating to support a firmware backed interface */
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if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO))
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return false;
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raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags);
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return true;
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}
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static inline void mpam_mon_sel_unlock(struct mpam_msc *msc)
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{
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raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags);
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}
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static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc)
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{
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lockdep_assert_held_once(&msc->_mon_sel_lock);
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}
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static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc)
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{
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raw_spin_lock_init(&msc->_mon_sel_lock);
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}
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struct mpam_class {
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/* mpam_components in this class */
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struct list_head components;
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cpumask_t affinity;
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u8 level;
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enum mpam_class_types type;
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/* member of mpam_classes */
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struct list_head classes_list;
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struct mpam_garbage garbage;
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};
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struct mpam_component {
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u32 comp_id;
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/* mpam_vmsc in this component */
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struct list_head vmsc;
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cpumask_t affinity;
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/* member of mpam_class:components */
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struct list_head class_list;
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/* parent: */
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struct mpam_class *class;
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struct mpam_garbage garbage;
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};
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struct mpam_vmsc {
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/* member of mpam_component:vmsc_list */
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struct list_head comp_list;
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/* mpam_msc_ris in this vmsc */
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struct list_head ris;
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/* All RIS in this vMSC are members of this MSC */
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struct mpam_msc *msc;
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/* parent: */
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struct mpam_component *comp;
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struct mpam_garbage garbage;
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};
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struct mpam_msc_ris {
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u8 ris_idx;
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cpumask_t affinity;
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/* member of mpam_vmsc:ris */
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struct list_head vmsc_list;
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/* member of mpam_msc:ris */
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struct list_head msc_list;
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/* parent: */
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struct mpam_vmsc *vmsc;
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struct mpam_garbage garbage;
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};
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/* List of all classes - protected by srcu*/
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extern struct srcu_struct mpam_srcu;
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extern struct list_head mpam_classes;
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/* System wide partid/pmg values */
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extern u16 mpam_partid_max;
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extern u8 mpam_pmg_max;
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/* Scheduled work callback to enable mpam once all MSC have been probed */
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void mpam_enable(struct work_struct *work);
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void mpam_disable(struct work_struct *work);
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int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level,
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cpumask_t *affinity);
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/*
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* MPAM MSCs have the following register layout. See:
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* Arm Memory System Resource Partitioning and Monitoring (MPAM) System
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* Component Specification.
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* https://developer.arm.com/documentation/ihi0099/aa/
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*/
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#define MPAM_ARCHITECTURE_V1 0x10
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/* Memory mapped control pages */
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/* ID Register offsets in the memory mapped page */
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#define MPAMF_IDR 0x0000 /* features id register */
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#define MPAMF_IIDR 0x0018 /* implementer id register */
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#define MPAMF_AIDR 0x0020 /* architectural id register */
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#define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */
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#define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */
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#define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */
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#define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */
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#define MPAMF_PRI_IDR 0x0048 /* priority partitioning */
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#define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */
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#define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */
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#define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */
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#define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */
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/* Configuration and Status Register offsets in the memory mapped page */
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#define MPAMCFG_PART_SEL 0x0100 /* partid to configure */
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#define MPAMCFG_CPBM 0x1000 /* cache-portion config */
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#define MPAMCFG_CMAX 0x0108 /* cache-capacity config */
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#define MPAMCFG_CMIN 0x0110 /* cache-capacity config */
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#define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */
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#define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */
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#define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */
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#define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */
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#define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */
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#define MPAMCFG_PRI 0x0400 /* priority partitioning config */
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#define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */
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#define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */
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#define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */
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#define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */
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#define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */
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#define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */
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#define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */
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#define MSMON_CSU 0x0840 /* current cache-usage */
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#define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */
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#define MSMON_MBWU 0x0860 /* current mem-bw usage value */
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#define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */
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#define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */
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#define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */
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#define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */
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#define MPAMF_ESR 0x00F8 /* error status register */
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#define MPAMF_ECR 0x00F0 /* error control register */
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/* MPAMF_IDR - MPAM features ID register */
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#define MPAMF_IDR_PARTID_MAX GENMASK(15, 0)
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#define MPAMF_IDR_PMG_MAX GENMASK(23, 16)
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#define MPAMF_IDR_HAS_CCAP_PART BIT(24)
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#define MPAMF_IDR_HAS_CPOR_PART BIT(25)
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#define MPAMF_IDR_HAS_MBW_PART BIT(26)
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#define MPAMF_IDR_HAS_PRI_PART BIT(27)
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#define MPAMF_IDR_EXT BIT(28)
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#define MPAMF_IDR_HAS_IMPL_IDR BIT(29)
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#define MPAMF_IDR_HAS_MSMON BIT(30)
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#define MPAMF_IDR_HAS_PARTID_NRW BIT(31)
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#define MPAMF_IDR_HAS_RIS BIT(32)
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#define MPAMF_IDR_HAS_EXTD_ESR BIT(38)
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#define MPAMF_IDR_HAS_ESR BIT(39)
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#define MPAMF_IDR_RIS_MAX GENMASK(59, 56)
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/* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */
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#define MPAMF_MSMON_IDR_MSMON_CSU BIT(16)
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#define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17)
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#define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31)
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/* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */
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#define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0)
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/* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */
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#define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0)
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#define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8)
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#define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28)
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#define MPAMF_CCAP_IDR_HAS_CMIN BIT(29)
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#define MPAMF_CCAP_IDR_NO_CMAX BIT(30)
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#define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31)
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/* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */
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#define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0)
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#define MPAMF_MBW_IDR_HAS_MIN BIT(10)
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#define MPAMF_MBW_IDR_HAS_MAX BIT(11)
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#define MPAMF_MBW_IDR_HAS_PBM BIT(12)
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#define MPAMF_MBW_IDR_HAS_PROP BIT(13)
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#define MPAMF_MBW_IDR_WINDWR BIT(14)
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#define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16)
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/* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */
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#define MPAMF_PRI_IDR_HAS_INTPRI BIT(0)
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#define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1)
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#define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4)
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#define MPAMF_PRI_IDR_HAS_DSPRI BIT(16)
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#define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17)
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#define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20)
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/* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */
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#define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0)
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#define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24)
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#define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25)
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#define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26)
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#define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27)
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#define MPAMF_CSUMON_IDR_HAS_XCL BIT(29)
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#define MPAMF_CSUMON_IDR_CSU_RO BIT(30)
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#define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31)
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/* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */
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#define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0)
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#define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28)
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#define MPAMF_MBWUMON_IDR_LWD BIT(29)
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#define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30)
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#define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31)
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/* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */
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#define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0)
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/* MPAMF_IIDR - MPAM implementation ID register */
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#define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0)
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#define MPAMF_IIDR_REVISION GENMASK(15, 12)
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#define MPAMF_IIDR_VARIANT GENMASK(19, 16)
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#define MPAMF_IIDR_PRODUCTID GENMASK(31, 20)
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/* MPAMF_AIDR - MPAM architecture ID register */
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#define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0)
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#define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4)
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/* MPAMCFG_PART_SEL - MPAM partition configuration selection register */
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#define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0)
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#define MPAMCFG_PART_SEL_INTERNAL BIT(16)
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#define MPAMCFG_PART_SEL_RIS GENMASK(27, 24)
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/* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */
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#define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0)
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/* MPAMCFG_CMAX - MPAM cache capacity configuration register */
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#define MPAMCFG_CMAX_SOFTLIM BIT(31)
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#define MPAMCFG_CMAX_CMAX GENMASK(15, 0)
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/* MPAMCFG_CMIN - MPAM cache capacity configuration register */
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#define MPAMCFG_CMIN_CMIN GENMASK(15, 0)
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/*
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* MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration
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* register
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*/
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#define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0)
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/*
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* MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration
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* register
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*/
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#define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0)
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#define MPAMCFG_MBW_MAX_HARDLIM BIT(31)
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/*
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* MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width
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* register
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*/
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#define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0)
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#define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8)
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/* MPAMCFG_PRI - MPAM priority partitioning configuration register */
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#define MPAMCFG_PRI_INTPRI GENMASK(15, 0)
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#define MPAMCFG_PRI_DSPRI GENMASK(31, 16)
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/*
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* MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning
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* configuration register
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*/
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#define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0)
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#define MPAMCFG_MBW_PROP_EN BIT(31)
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/*
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* MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register
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*/
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#define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0)
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#define MPAMCFG_INTPARTID_INTERNAL BIT(16)
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/* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */
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#define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0)
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#define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24)
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/* MPAMF_ESR - MPAM Error Status Register */
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#define MPAMF_ESR_PARTID_MON GENMASK(15, 0)
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#define MPAMF_ESR_PMG GENMASK(23, 16)
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#define MPAMF_ESR_ERRCODE GENMASK(27, 24)
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#define MPAMF_ESR_OVRWR BIT(31)
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#define MPAMF_ESR_RIS GENMASK(35, 32)
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/* MPAMF_ECR - MPAM Error Control Register */
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#define MPAMF_ECR_INTEN BIT(0)
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/* Error conditions in accessing memory mapped registers */
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#define MPAM_ERRCODE_NONE 0
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#define MPAM_ERRCODE_PARTID_SEL_RANGE 1
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#define MPAM_ERRCODE_REQ_PARTID_RANGE 2
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#define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3
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#define MPAM_ERRCODE_REQ_PMG_RANGE 4
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#define MPAM_ERRCODE_MONITOR_RANGE 5
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#define MPAM_ERRCODE_INTPARTID_RANGE 6
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#define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7
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#define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8
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#define MPAM_ERRCODE_RIS_NO_CONTROL 9
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#define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10
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#define MPAM_ERRCODE_RIS_NO_MONITOR 11
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/*
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* MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage
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* usage monitor control register
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* MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory
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* bandwidth usage monitor control register
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*/
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#define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0)
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#define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15)
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#define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16)
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#define MSMON_CFG_x_CTL_MATCH_PMG BIT(17)
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#define MSMON_CFG_MBWU_CTL_SCLEN BIT(19)
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#define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20)
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#define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24)
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#define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25)
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#define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26)
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#define MSMON_CFG_x_CTL_CAPT_RESET BIT(27)
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#define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28)
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#define MSMON_CFG_x_CTL_EN BIT(31)
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#define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42
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#define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43
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/*
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* MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage
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* usage monitor filter register
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* MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory
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* bandwidth usage monitor filter register
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*/
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#define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0)
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#define MSMON_CFG_x_FLT_PMG GENMASK(23, 16)
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#define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30)
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#define MSMON_CFG_CSU_FLT_XCL BIT(31)
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/*
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* MSMON_CSU - Memory system performance monitor cache storage usage monitor
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* register
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* MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage
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* capture register
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* MSMON_MBWU - Memory system performance monitor memory bandwidth usage
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* monitor register
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* MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage
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* capture register
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*/
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#define MSMON___VALUE GENMASK(30, 0)
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#define MSMON___NRDY BIT(31)
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#define MSMON___L_NRDY BIT(63)
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#define MSMON___L_VALUE GENMASK(43, 0)
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#define MSMON___LWD_VALUE GENMASK(62, 0)
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/*
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* MSMON_CAPT_EVNT - Memory system performance monitoring capture event
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* generation register
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*/
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#define MSMON_CAPT_EVNT_NOW BIT(0)
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#endif /* MPAM_INTERNAL_H */
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