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linux/drivers/gpu/drm/amd/display/dc/dcn20
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George Shen ab2cf4c86b drm/amd/display: Change null plane state swizzle mode to 4kb_s 
[Why]
During SetPathMode and UpdatePlanes, the plane state can be null. We default
to linear swizzle mode when plane state is null. This resulted in bandwidth
validation failing when trying to set 8K60 mode (which previously passed validation
during rebuild timing list).

[How]
Change the default swizzle mode from linear to 4kb_s and update pitch accordingly.

Signed-off-by: George Shen <george.shen@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 		2020-08-06 16:49:29 -04:00
..
Makefile amdgpu: Enable initial DCN support on POWER 2019-12-18 16:09:05 -05:00
dcn20_dccg.c drm/amd/display: DPP DTO isn't update properly. 2020-03-19 00:03:04 -04:00
dcn20_dccg.h drm/amd/display: Add DCN3 DCCG 2020-07-01 01:59:14 -04:00
dcn20_dpp.c drm/amd/display: correct alpha_en programming for new pixel format 2020-07-01 01:59:19 -04:00
dcn20_dpp.h drm/amd/display: Indirect reg read macro with shift and mask 2020-01-16 14:13:53 -05:00
dcn20_dpp_cm.c drm/amd/display: Indirect reg read macro with shift and mask 2020-01-16 14:13:53 -05:00
dcn20_dsc.c drm/amd/display: Rename bytes_pp to the correct bits_pp 2020-08-06 16:37:47 -04:00
dcn20_dsc.h drm/amd/display: Remove Unused Registers 2020-07-01 01:59:15 -04:00
dcn20_dwb.c
…
dcn20_dwb.h
…
dcn20_dwb_scl.c
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dcn20_hubbub.c drm/amd/display: Add DCN3 HUBHUB 2020-07-01 01:59:14 -04:00
dcn20_hubbub.h drm/amd/display: correct rn NUM_VMID 2020-05-21 12:48:43 -04:00
dcn20_hubp.c drm/amd/display: Add DCN3 HUBP 2020-07-01 01:59:14 -04:00
dcn20_hubp.h drm/amd/display: Add DCN3 HUBP 2020-07-01 01:59:14 -04:00
dcn20_hwseq.c drm/amd/display: Allow asic specific FSFT timing optimization 2020-08-06 16:40:18 -04:00
dcn20_hwseq.h drm/amd/display: Allow asic specific FSFT timing optimization 2020-08-06 16:40:18 -04:00
dcn20_init.c drm/amd/display: Allow asic specific FSFT timing optimization 2020-08-06 16:40:18 -04:00
dcn20_init.h drm/amd/display: cleanup of function pointer tables 2019-11-19 10:12:53 -05:00
dcn20_link_encoder.c drm/amd/display: Read VBIOS Golden Settings Tbl 2020-08-06 16:47:13 -04:00
dcn20_link_encoder.h drm/amd/display: Read VBIOS Golden Settings Tbl 2020-08-06 16:47:13 -04:00
dcn20_mmhubbub.c
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dcn20_mmhubbub.h drm/amd/display: Update register defines 2020-02-11 11:50:18 -05:00
dcn20_mpc.c drm/amd/display: Use cursor locking to prevent flip delays 2020-04-28 16:19:56 -04:00
dcn20_mpc.h drm/amd/display: Use cursor locking to prevent flip delays 2020-04-28 16:19:56 -04:00
dcn20_opp.c drm/amd/display: program DPG_OFFSET_SEGMENT for odm_pipe 2020-03-05 00:29:47 -05:00
dcn20_opp.h drm/amd/display: program DPG_OFFSET_SEGMENT for odm_pipe 2020-03-05 00:29:47 -05:00
dcn20_optc.c drm/amd/display: add optc get crc support for timings with ODM/DSC 2020-04-22 18:11:47 -04:00
dcn20_optc.h drm/amd/display: add optc get crc support for timings with ODM/DSC 2020-04-22 18:11:47 -04:00
dcn20_resource.c drm/amd/display: Change null plane state swizzle mode to 4kb_s 2020-08-06 16:49:29 -04:00
dcn20_resource.h drm/amd/display: fix and simplify pipe split logic 2020-05-21 12:48:43 -04:00
dcn20_stream_encoder.c drm/amd/display: Improve compatibility by re-ordering info-packets 2020-07-21 15:37:39 -04:00
dcn20_stream_encoder.h
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dcn20_vmid.c
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dcn20_vmid.h drm/amd/display: Update register defines 2020-02-11 11:50:18 -05:00