linux/drivers/gpu/drm/amd/include/asic_reg/gc
Alex Sierra 4b27a33c3b drm/amdgpu: Force order between a read and write to the same address
Setting register to force ordering to prevent read/write or write/read
hazards for un-cached modes.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.1.x
2023-11-29 17:57:33 -05:00
..
gc_9_0_default.h
gc_9_0_offset.h
gc_9_0_sh_mask.h
gc_9_1_offset.h
gc_9_1_sh_mask.h
gc_9_2_1_offset.h
gc_9_2_1_sh_mask.h
gc_9_4_1_offset.h
gc_9_4_1_sh_mask.h
gc_9_4_2_offset.h
gc_9_4_2_sh_mask.h
gc_9_4_3_offset.h drm/amdgpu: Add gc v9_4_3 ras error status registers 2023-06-09 10:37:34 -04:00
gc_9_4_3_sh_mask.h drm/amdgpu: Add gc v9_4_3 ras error status registers 2023-06-09 10:37:34 -04:00
gc_10_1_0_default.h
gc_10_1_0_offset.h drm/amdgpu: setup hw debug registers on driver initialization 2023-06-09 12:34:56 -04:00
gc_10_1_0_sh_mask.h drm/amdgpu: setup hw debug registers on driver initialization 2023-06-09 12:34:56 -04:00
gc_10_3_0_default.h
gc_10_3_0_offset.h drm/amdgpu: setup hw debug registers on driver initialization 2023-06-09 12:34:56 -04:00
gc_10_3_0_sh_mask.h drm/amdgpu: setup hw debug registers on driver initialization 2023-06-09 12:34:56 -04:00
gc_11_0_0_default.h
gc_11_0_0_offset.h drm/amdgpu: Force order between a read and write to the same address 2023-11-29 17:57:33 -05:00
gc_11_0_0_sh_mask.h drm/amdgpu: setup hw debug registers on driver initialization 2023-06-09 12:34:56 -04:00
gc_11_0_3_offset.h amd/amdgpu: Add RLC_RLCS_FED_STATUS_* to gc v11_0_3 ip headers 2023-01-17 16:11:50 -05:00
gc_11_0_3_sh_mask.h amd/amdgpu: Add RLC_RLCS_FED_STATUS_* to gc v11_0_3 ip headers 2023-01-17 16:11:50 -05:00
gc_11_5_0_offset.h drm/amdgpu: add gc headers for gc 11.5.0 2023-08-30 15:00:34 -04:00
gc_11_5_0_sh_mask.h drm/amdgpu: update to the latest GC 11.5 headers 2023-10-19 18:26:51 -04:00