linux/drivers/gpu/drm/amd/display/dc/clk_mgr
Dillon Varone 4f5b8d78ca drm/amd/display: Init DPPCLK from SMU on dcn32
[WHY & HOW]
DPPCLK ranges should be obtained from the SMU when available.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-03-20 13:12:58 -04:00
..
dce60
dce100 drm/amd/display: Initialize variable with default value 2024-02-22 10:14:34 -05:00
dce110
dce112 drm/amd/display: Clean FPGA code in dc 2023-06-09 10:44:11 -04:00
dce120 drm/amd/display: Refactor HWSS into component folder 2023-10-09 17:00:09 -04:00
dcn10 drm/amd/display: Drop unnecessary header 2024-02-22 10:26:08 -05:00
dcn20 drm/amd/display: apply edge-case DISPCLK WDIVIDER changes to master OTG pipes only 2023-10-04 18:41:25 -04:00
dcn21 drm/amd/display: Add SMU timeout check and retry 2024-02-22 10:14:53 -05:00
dcn30 drm/amd/display: Clean FPGA code in dc 2023-06-09 10:44:11 -04:00
dcn31 drm/amd/display: Drop legacy code 2024-02-07 12:26:23 -05:00
dcn32 drm/amd/display: Init DPPCLK from SMU on dcn32 2024-03-20 13:12:58 -04:00
dcn35 drm/amd/display: allow psr-su/replay for z8 2024-02-14 17:15:01 -05:00
dcn201 drm/amd/display: switch DC over to the new DRM logging macros 2023-09-26 17:00:21 -04:00
dcn301 drm/amd/display: Add SMU timeout check and retry 2024-02-22 10:14:53 -05:00
dcn314 drm/amd/display: Drop legacy code 2024-02-07 12:26:23 -05:00
dcn315 drm/amd/display: Drop legacy code 2024-02-07 12:26:23 -05:00
dcn316 drm/amd/display: Drop legacy code 2024-02-07 12:26:23 -05:00
Makefile drm/amd/display: Add DCN35 CLK_MGR 2023-08-30 15:51:15 -04:00
clk_mgr.c drm/amd/display: Drop unnecessary header 2024-02-22 10:26:08 -05:00