linux/arch/arc/include/asm
Alexey Brodkin f51e2f1911 ARC: make sure instruction_pointer() returns unsigned value
Currently instruction_pointer() returns pt_regs->ret and so return value
is of type "long", which implicitly stands for "signed long".

While that's perfectly fine when dealing with 32-bit values if return
value of instruction_pointer() gets assigned to 64-bit variable sign
extension may happen.

And at least in one real use-case it happens already.
In perf_prepare_sample() return value of perf_instruction_pointer()
(which is an alias to instruction_pointer() in case of ARC) is assigned
to (struct perf_sample_data)->ip (which type is "u64").

And what we see if instuction pointer points to user-space application
that in case of ARC lays below 0x8000_0000 "ip" gets set properly with
leading 32 zeros. But if instruction pointer points to kernel address
space that starts from 0x8000_0000 then "ip" is set with 32 leadig
"f"-s. I.e. id instruction_pointer() returns 0x8100_0000, "ip" will be
assigned with 0xffff_ffff__8100_0000. Which is obviously wrong.

In particular that issuse broke output of perf, because perf was unable
to associate addresses like 0xffff_ffff__8100_0000 with anything from
/proc/kallsyms.

That's what we used to see:
 ----------->8----------
  6.27%  ls       [unknown]                [k] 0xffffffff8046c5cc
  2.96%  ls       libuClibc-0.9.34-git.so  [.] memcpy
  2.25%  ls       libuClibc-0.9.34-git.so  [.] memset
  1.66%  ls       [unknown]                [k] 0xffffffff80666536
  1.54%  ls       libuClibc-0.9.34-git.so  [.] 0x000224d6
  1.18%  ls       libuClibc-0.9.34-git.so  [.] 0x00022472
 ----------->8----------

With that change perf output looks much better now:
 ----------->8----------
  8.21%  ls       [kernel.kallsyms]        [k] memset
  3.52%  ls       libuClibc-0.9.34-git.so  [.] memcpy
  2.11%  ls       libuClibc-0.9.34-git.so  [.] malloc
  1.88%  ls       libuClibc-0.9.34-git.so  [.] memset
  1.64%  ls       [kernel.kallsyms]        [k] _raw_spin_unlock_irqrestore
  1.41%  ls       [kernel.kallsyms]        [k] __d_lookup_rcu
 ----------->8----------

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: arc-linux-dev@synopsys.com
Cc: stable@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-07-13 13:33:18 +05:30
..
Kbuild - Support for HS38 cores based on ARCv2 ISA 2015-07-01 09:24:26 -07:00
arcregs.h ARCv2: MMUv4: cache programming model changes 2015-06-22 14:06:55 +05:30
asm-offsets.h
atomic.h ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock 2015-06-25 06:00:18 +05:30
barrier.h ARCv2: barriers 2015-06-25 06:00:17 +05:30
bitops.h ARC: Make ARC bitops "safer" (add anti-optimization) 2015-07-09 17:36:32 +05:30
bug.h
cache.h ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency) 2015-06-25 06:00:19 +05:30
cacheflush.h ARC: fold ___flush_dcache_page into __flush_dcache_page 2015-05-19 11:27:13 +05:30
checksum.h
clk.h
cmpxchg.h ARC: add smp barriers around atomics per Documentation/atomic_ops.txt 2015-06-25 06:00:16 +05:30
current.h
delay.h ARCv2: Adhere to Zero Delay loop restriction 2015-06-22 14:06:56 +05:30
disasm.h
dma-mapping.h Merge branch 'akpm' (patches from Andrew) 2015-07-01 17:47:51 -07:00
dma.h
elf.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
entry-arcv2.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
entry-compact.h ARC: intc: split into ARCompact ISA specific, common bits 2015-06-19 18:09:40 +05:30
entry.h ARCv2: STAR 9000808988: signals involving Delay Slot 2015-06-22 14:06:55 +05:30
exec.h
futex.h ARC: Add llock/scond to futex backend 2015-07-09 17:36:33 +05:30
io.h - Support for HS38 cores based on ARCv2 ISA 2015-07-01 09:24:26 -07:00
irq.h ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al 2015-06-22 14:06:56 +05:30
irqflags-arcv2.h ARCv2: STAR 9000814690: Really Re-enable interrupts to avoid deadlocks 2015-06-22 14:06:55 +05:30
irqflags-compact.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
irqflags.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
kdebug.h
kgdb.h
kprobes.h
linkage.h
mach_desc.h
mcip.h ARCv2: SMP: clocksource: Enable Global Real Time counter 2015-06-22 14:06:57 +05:30
mm-arch-hooks.h mm: new mm hook framework 2015-06-24 17:49:41 -07:00
mmu.h ARCv2: MMUv4: TLB programming Model changes 2015-06-22 14:06:55 +05:30
mmu_context.h
module.h
mutex.h
page.h
perf_event.h ARC: perf: support cache hit/miss ratio 2015-04-20 18:27:34 +05:30
pgalloc.h
pgtable.h ARCv2: MMUv4: TLB programming Model changes 2015-06-22 14:06:55 +05:30
processor.h ARC: mm: document system mem map clearly 2015-06-19 18:09:29 +05:30
ptrace.h ARC: make sure instruction_pointer() returns unsigned value 2015-07-13 13:33:18 +05:30
sections.h
segment.h
serial.h ARC: Dynamically determine BASE_BAUD from DeviceTree 2015-02-02 17:08:37 +05:30
setup.h
shmparam.h
smp.h
spinlock.h ARC: add smp barriers around atomics per Documentation/atomic_ops.txt 2015-06-25 06:00:16 +05:30
spinlock_types.h
stacktrace.h ARC: Make arc_unwind_core accessible externally 2015-02-27 10:15:00 +05:30
string.h
switch_to.h
syscall.h
syscalls.h
thread_info.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
timex.h
tlb-mmu1.h
tlb.h
tlbflush.h
uaccess.h ARCv2: Adhere to Zero Delay loop restriction 2015-06-22 14:06:56 +05:30
unaligned.h
unwind.h