mirror of https://github.com/torvalds/linux.git
69c32972d5
This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4 counters. All counters lack overflow interrupt and are sampled periodically. Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> [will: consistent enum cpuhp_state naming] Signed-off-by: Will Deacon <will.deacon@arm.com> |
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| .. | ||
| hisilicon | ||
| Kconfig | ||
| Makefile | ||
| arm-cci.c | ||
| arm-ccn.c | ||
| arm_dsu_pmu.c | ||
| arm_pmu.c | ||
| arm_pmu_acpi.c | ||
| arm_pmu_platform.c | ||
| arm_spe_pmu.c | ||
| qcom_l2_pmu.c | ||
| qcom_l3_pmu.c | ||
| thunderx2_pmu.c | ||
| xgene_pmu.c | ||