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linux/arch/xtensa
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Max Filippov 839769c354 xtensa: fix a7 clobbering in coprocessor context load/store 
Fast coprocessor exception handler saves a3..a6, but coprocessor context
load/store code uses a4..a7 as temporaries, potentially clobbering a7.
'Potentially' because coprocessor state load/store macros may not use
all four temporary registers (and neither FPU nor HiFi macros do).
Use a3..a6 as intended.

Cc: stable@vger.kernel.org
Fixes: c658eac628 ("[XTENSA] Add support for configurable registers and coprocessors")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
 		2022-04-15 18:44:02 -07:00
..
boot xtensa: fix DTC warning unit_address_format 2022-03-17 02:55:47 -07:00
configs rcu: Fix undefined Kconfig macros 2021-09-13 16:32:46 -07:00
include TTY/Serial driver changes for 5.18-rc1 2022-03-28 13:00:51 -07:00
kernel xtensa: fix a7 clobbering in coprocessor context load/store 2022-04-15 18:44:02 -07:00
lib xtensa: add helpers for division, remainder and shifts 2022-03-09 14:02:40 -08:00
mm xtensa: define update_mmu_tlb function 2022-03-22 09:45:09 -07:00
platforms arch: xtensa: platforms: Fix deadlock in rs_close() 2022-04-13 03:36:34 -07:00
variants
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Kbuild
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Kconfig dma-mapping updates for Linux 5.18 2022-03-29 08:50:14 -07:00
Kconfig.debug
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Makefile xtensa: add kernel ABI selection to Kconfig 2022-03-09 14:16:35 -08:00