Like Xu 488e13a489 perf/x86/lbr: Remove cpuc->lbr_xsave allocation from atomic context ... If the kernel is compiled with the CONFIG_LOCKDEP option, the conditional might_sleep_if() deep in kmem_cache_alloc() will generate the following trace, and potentially cause a deadlock when another LBR event is added: [] BUG: sleeping function called from invalid context at include/linux/sched/mm.h:196 [] Call Trace: [] kmem_cache_alloc+0x36/0x250 [] intel_pmu_lbr_add+0x152/0x170 [] x86_pmu_add+0x83/0xd0 Make it symmetric with the release_lbr_buffers() call and mirror the existing DS buffers. Fixes: c085fb8774 ("perf/x86/intel/lbr: Support XSAVES for arch LBR read") Signed-off-by: Like Xu <like.xu@linux.intel.com> [peterz: simplified] Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Kan Liang <kan.liang@linux.intel.com> Link: https://lkml.kernel.org/r/20210430052247.3079672-2-like.xu@linux.intel.com		2021-05-18 12:53:47 +02:00
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amd	Handle power-gating of AMD IOMMU perf counters properly when they are used.	2021-05-09 13:00:26 -07:00
intel	perf/x86/lbr: Remove cpuc->lbr_xsave allocation from atomic context	2021-05-18 12:53:47 +02:00
zhaoxin	x86: Fix various typos in comments	2021-03-18 15:31:53 +01:00
Kconfig	treewide: replace '---help---' in Kconfig files with 'help'	2020-06-14 01:57:21 +09:00
Makefile	perf/x86/rapl: Fix RAPL config variable bug	2020-06-02 11:52:56 +02:00
core.c	perf/x86/lbr: Remove cpuc->lbr_xsave allocation from atomic context	2021-05-18 12:53:47 +02:00
msr.c	perf/x86/msr: Add Alder Lake CPU support	2021-04-19 20:03:29 +02:00
perf_event.h	perf/x86/lbr: Remove cpuc->lbr_xsave allocation from atomic context	2021-05-18 12:53:47 +02:00
probe.c	perf/x86/rapl: Add msr mask support	2021-02-10 14:44:54 +01:00
probe.h	perf/x86/rapl: Add msr mask support	2021-02-10 14:44:54 +01:00
rapl.c	perf/x86/rapl: Add support for Intel Alder Lake	2021-04-19 20:03:30 +02:00