mirror of https://github.com/torvalds/linux.git
0c7ea2b1c8
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|---|---|---|
| .. | ||
| Kconfig | ||
| Makefile | ||
| clk-audio-sync.c | ||
| clk-bpmp.c | ||
| clk-dfll.c | ||
| clk-dfll.h | ||
| clk-divider.c | ||
| clk-id.h | ||
| clk-periph-fixed.c | ||
| clk-periph-gate.c | ||
| clk-periph.c | ||
| clk-pll-out.c | ||
| clk-pll.c | ||
| clk-sdmmc-mux.c | ||
| clk-super.c | ||
| clk-tegra-audio.c | ||
| clk-tegra-fixed.c | ||
| clk-tegra-periph.c | ||
| clk-tegra-super-cclk.c | ||
| clk-tegra-super-gen4.c | ||
| clk-tegra20-emc.c | ||
| clk-tegra20.c | ||
| clk-tegra30.c | ||
| clk-tegra114.c | ||
| clk-tegra124-dfll-fcpu.c | ||
| clk-tegra124-emc.c | ||
| clk-tegra124.c | ||
| clk-tegra210-emc.c | ||
| clk-tegra210.c | ||
| clk-utils.c | ||
| clk.c | ||
| clk.h | ||
| cvb.c | ||
| cvb.h | ||