Christoph Hellwig 9209fb5189 riscv: move sifive_l2_cache.c to drivers/soc ... The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/soc and add a Kconfig option for it, as well as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. Fixes: a967a289f1 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Borislav Petkov <bp@suse.de> [paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-12-20 03:40:24 -08:00
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actions	…
amlogic	…
aspeed	…
atmel	…
bcm	…
dove	…
fsl	…
gemini	…
imx	…
ixp4xx	…
lantiq	…
mediatek	Merge mainline/master into arm/fixes	2019-12-05 13:18:54 -08:00
qcom	drm msm + fixes for 5.5-rc1	2019-12-06 10:28:09 -08:00
renesas	…
rockchip	…
samsung	…
sifive	riscv: move sifive_l2_cache.c to drivers/soc	2019-12-20 03:40:24 -08:00
sunxi	…
tegra	soc/tegra: Fixes for v5.5-rc1	2019-12-06 08:28:38 -08:00
ti	…
ux500	…
versatile	…
xilinx	…
zte	…
Kconfig	riscv: move sifive_l2_cache.c to drivers/soc	2019-12-20 03:40:24 -08:00
Makefile	riscv: move sifive_l2_cache.c to drivers/soc	2019-12-20 03:40:24 -08:00