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[Why] When link training fails, the phy clock will be disabled. However, in enable_streams, it is assumed that link training succeeded and the mux selects the phy clock, causing a hang when a register write is made. [How] When enable_stream is hit, check if link training failed. If it did, fall back to the ref clock to avoid a hang and keep the system in a recoverable state. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Brendan Tam <Brendan.Tam@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org |
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| dce | ||
| dce80 | ||
| dce100 | ||
| dce110 | ||
| dce112 | ||
| dce120 | ||
| dcn10 | ||
| dcn20 | ||
| dcn21 | ||
| dcn30 | ||
| dcn31 | ||
| dcn32 | ||
| dcn35 | ||
| dcn201 | ||
| dcn301 | ||
| dcn302 | ||
| dcn303 | ||
| dcn314 | ||
| dcn351 | ||
| dcn401 | ||
| Makefile | ||
| hw_sequencer.h | ||
| hw_sequencer_private.h | ||