linux/arch/arm64/include
Paolo Bonzini 7d862707d6 KVM/arm64 changes for 6.17, round #3
- Invalidate nested MMUs upon freeing the PGD to avoid WARNs when
    visiting from an MMU notifier
 
  - Fixes to the TLB match process and TLB invalidation range for
    managing the VCNR pseudo-TLB
 
  - Prevent SPE from erroneously profiling guests due to UNKNOWN reset
    values in PMSCR_EL1
 
  - Fix save/restore of host MDCR_EL2 to account for eagerly programming
    at vcpu_load() on VHE systems
 
  - Correct lock ordering when dealing with VGIC LPIs, avoiding scenarios
    where an xarray's spinlock was nested with a *raw* spinlock
 
  - Permit stage-2 read permission aborts which are possible in the case
    of NV depending on the guest hypervisor's stage-2 translation
 
  - Call raw_spin_unlock() instead of the internal spinlock API
 
  - Fix parameter ordering when assigning VBAR_EL1
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Merge tag 'kvmarm-fixes-6.17-2' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/arm64 changes for 6.17, round #3

 - Invalidate nested MMUs upon freeing the PGD to avoid WARNs when
   visiting from an MMU notifier

 - Fixes to the TLB match process and TLB invalidation range for
   managing the VCNR pseudo-TLB

 - Prevent SPE from erroneously profiling guests due to UNKNOWN reset
   values in PMSCR_EL1

 - Fix save/restore of host MDCR_EL2 to account for eagerly programming
   at vcpu_load() on VHE systems

 - Correct lock ordering when dealing with VGIC LPIs, avoiding scenarios
   where an xarray's spinlock was nested with a *raw* spinlock

 - Permit stage-2 read permission aborts which are possible in the case
   of NV depending on the guest hypervisor's stage-2 translation

 - Call raw_spin_unlock() instead of the internal spinlock API

 - Fix parameter ordering when assigning VBAR_EL1
2025-09-17 19:44:40 +02:00
..
asm KVM/arm64 changes for 6.17, round #3 2025-09-17 19:44:40 +02:00
uapi/asm arm64: uapi: Provide correct __BITS_PER_LONG for the compat vDSO 2025-09-03 12:07:23 +01:00