mirror of https://github.com/torvalds/linux.git
81af9e40e2
According to internal documentation, on SM8650, when the PHY is configured
in Gear 4, the QPHY_V6_PCS_UFS_PLL_CNTL register needs to have the same
value as for Gear 5.
At the moment, there is no board that comes with a UFS 3.x device, so
this issue doesn't show up, but with the new Eliza SoC, which uses the
same init sequence as SM8650, on the MTP board, the link startup fails
with the current Gear 4 PCS table.
So fix that by moving the entry into the PCS generic table instead,
while keeping the value from Gear 5 configuration.
Cc: stable@vger.kernel.org # v6.10
Fixes:
|
||
|---|---|---|
| .. | ||
| allwinner | ||
| amlogic | ||
| apple | ||
| broadcom | ||
| cadence | ||
| freescale | ||
| hisilicon | ||
| ingenic | ||
| intel | ||
| lantiq | ||
| marvell | ||
| mediatek | ||
| microchip | ||
| motorola | ||
| mscc | ||
| nuvoton | ||
| qualcomm | ||
| ralink | ||
| realtek | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| socionext | ||
| sophgo | ||
| spacemit | ||
| st | ||
| starfive | ||
| sunplus | ||
| tegra | ||
| ti | ||
| xilinx | ||
| Kconfig | ||
| Makefile | ||
| phy-airoha-pcie-regs.h | ||
| phy-airoha-pcie.c | ||
| phy-can-transceiver.c | ||
| phy-common-props-test.c | ||
| phy-common-props.c | ||
| phy-core-mipi-dphy.c | ||
| phy-core.c | ||
| phy-google-usb.c | ||
| phy-lgm-usb.c | ||
| phy-lpc18xx-usb-otg.c | ||
| phy-nxp-ptn3222.c | ||
| phy-pistachio-usb.c | ||
| phy-snps-eusb2.c | ||
| phy-spacemit-k1-pcie.c | ||
| phy-xgene.c | ||