mirror of https://github.com/torvalds/linux.git
56 lines
1.5 KiB
Rust
56 lines
1.5 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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use crate::driver::Bar0;
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// TODO
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//
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// Create register definitions via generic macros. See task "Generic register
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// abstraction" in Documentation/gpu/nova/core/todo.rst.
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const BOOT0_OFFSET: usize = 0x00000000;
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// 3:0 - chipset minor revision
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const BOOT0_MINOR_REV_SHIFT: u8 = 0;
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const BOOT0_MINOR_REV_MASK: u32 = 0x0000000f;
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// 7:4 - chipset major revision
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const BOOT0_MAJOR_REV_SHIFT: u8 = 4;
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const BOOT0_MAJOR_REV_MASK: u32 = 0x000000f0;
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// 23:20 - chipset implementation Identifier (depends on architecture)
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const BOOT0_IMPL_SHIFT: u8 = 20;
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const BOOT0_IMPL_MASK: u32 = 0x00f00000;
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// 28:24 - chipset architecture identifier
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const BOOT0_ARCH_MASK: u32 = 0x1f000000;
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// 28:20 - chipset identifier (virtual register field combining BOOT0_IMPL and
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// BOOT0_ARCH)
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const BOOT0_CHIPSET_SHIFT: u8 = BOOT0_IMPL_SHIFT;
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const BOOT0_CHIPSET_MASK: u32 = BOOT0_IMPL_MASK | BOOT0_ARCH_MASK;
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#[derive(Copy, Clone)]
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pub(crate) struct Boot0(u32);
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impl Boot0 {
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#[inline]
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pub(crate) fn read(bar: &Bar0) -> Self {
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Self(bar.readl(BOOT0_OFFSET))
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}
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#[inline]
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pub(crate) fn chipset(&self) -> u32 {
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(self.0 & BOOT0_CHIPSET_MASK) >> BOOT0_CHIPSET_SHIFT
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}
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#[inline]
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pub(crate) fn minor_rev(&self) -> u8 {
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((self.0 & BOOT0_MINOR_REV_MASK) >> BOOT0_MINOR_REV_SHIFT) as u8
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}
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#[inline]
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pub(crate) fn major_rev(&self) -> u8 {
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((self.0 & BOOT0_MAJOR_REV_MASK) >> BOOT0_MAJOR_REV_SHIFT) as u8
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}
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}
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