Krzysztof Kozlowski 0699018b41 drm/msm/dsi/phy: Define PHY_CMN_CLK_CFG[01] bitfields and simplify saving ... Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to avoid hard-coding bit masks and shifts and make the code a bit more readable. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/638324/ Link: https://lore.kernel.org/r/20250219-drm-msm-phy-pll-cfg-reg-v5-2-d28973fa513a@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>		2025-02-26 12:15:49 +02:00
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dsi_phy.c	drm/msm/dsi: Add dsi phy support for SM6150	2024-12-15 14:37:20 +02:00
dsi_phy.h	drm/msm/dsi/phy: Use the header with clock IDs	2025-02-26 12:15:48 +02:00
dsi_phy_7nm.c	drm/msm/dsi/phy: Define PHY_CMN_CLK_CFG[01] bitfields and simplify saving	2025-02-26 12:15:49 +02:00
dsi_phy_10nm.c	drm/msm/dsi/phy: Use the header with clock IDs	2025-02-26 12:15:48 +02:00
dsi_phy_14nm.c	drm/msm/dsi/phy: Use the header with clock IDs	2025-02-26 12:15:48 +02:00
dsi_phy_20nm.c	drm/msm/dsi: Remove dsi_phy_read/write()	2024-06-23 01:15:39 +03:00
dsi_phy_28nm.c	drm/msm/dsi/phy: Use the header with clock IDs	2025-02-26 12:15:48 +02:00
dsi_phy_28nm_8960.c	drm/msm/dsi/phy: Use the header with clock IDs	2025-02-26 12:15:48 +02:00