linux/Documentation/admin-guide/perf
Yicong Yang 3b051bb7cb drivers/perf: hisi: Export associated CPUs of each PMU through sysfs
Although the event of the uncore PMU can only be opened on a single
CPU, some PMU does have the affinity on a range of CPUs. For example
the L3C PMU is associated to the CPUs sharing the L3T it monitors.
Users may infer this affinity by the PMU name which may have SCCL ID
and CCL ID encoded (for L3C etc), but it's not that straightforward.
So export this information by adding an "associated_cpus" sysfs
attribute then user can get this directly.

Reviewed-by: Jonathan Cameron <Joanthan.Cameron@huawei.com>
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Link: https://lore.kernel.org/r/20241210141525.37788-9-yangyicong@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>
2024-12-10 15:57:24 +00:00
..
alibaba_pmu.rst
ampere_cspmu.rst
arm-ccn.rst
arm-cmn.rst
arm-ni.rst perf: Add driver for Arm NI-700 interconnect PMU 2024-09-06 12:58:28 +01:00
arm_dsu_pmu.rst
cxl.rst
dwc_pcie_pmu.rst Documentation: dwc_pcie_pmu: Fix the mnemonics and eventid 2024-12-09 15:45:21 +00:00
hisi-pcie-pmu.rst drivers/perf: hisi_pcie: Export supported Root Ports [bdf_min, bdf_max] 2024-08-30 11:43:10 +01:00
hisi-pmu.rst drivers/perf: hisi: Export associated CPUs of each PMU through sysfs 2024-12-10 15:57:24 +00:00
hns3-pmu.rst
imx-ddr.rst
index.rst perf/marvell: Odyssey LLC-TAD performance monitor support 2024-12-09 15:57:49 +00:00
meson-ddr-pmu.rst
mrvl-odyssey-ddr-pmu.rst perf/marvell: Odyssey DDR Performance monitor support 2024-12-09 15:57:39 +00:00
mrvl-odyssey-tad-pmu.rst perf/marvell: Odyssey LLC-TAD performance monitor support 2024-12-09 15:57:49 +00:00
mrvl-pem-pmu.rst perf/marvell: Marvell PEM performance monitor support 2024-10-28 17:35:35 +00:00
nvidia-pmu.rst perf: arm_cspmu: nvidia: monitor all ports by default 2024-12-09 15:07:49 +00:00
qcom_l2_pmu.rst
qcom_l3_pmu.rst
starfive_starlink_pmu.rst
thunderx2-pmu.rst
xgene-pmu.rst