linux/drivers/clk/rockchip
Stephen Boyd 112104e2b7
Merge branch 'clk-determine-rate' into clk-next
* clk-determine-rate: (120 commits)
  clk: microchip: core: remove duplicate roclk_determine_rate()
  clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver
  clk: scmi: migrate round_rate() to determine_rate()
  clk: ti: fapll: convert from round_rate() to determine_rate()
  clk: ti: dra7-atl: convert from round_rate() to determine_rate()
  clk: ti: divider: convert from round_rate() to determine_rate()
  clk: ti: composite: convert from round_rate() to determine_rate()
  clk: ti: dpll: convert from round_rate() to determine_rate()
  clk: ti: dpll: change error return from ~0 to -EINVAL
  clk: ti: dpll: remove round_rate() in favor of determine_rate()
  clk: tegra: tegra210-emc: convert from round_rate() to determine_rate()
  clk: tegra: super: convert from round_rate() to determine_rate()
  clk: tegra: pll: convert from round_rate() to determine_rate()
  clk: tegra: periph: divider: convert from round_rate() to determine_rate()
  clk: tegra: divider: convert from round_rate() to determine_rate()
  clk: tegra: audio-sync: convert from round_rate() to determine_rate()
  clk: fixed-factor: drop round_rate() clk ops
  clk: divider: remove round_rate() in favor of determine_rate()
  clk: visconti: pll: convert from round_rate() to determine_rate()
  clk: versatile: vexpress-osc: convert from round_rate() to determine_rate()
  ...
2025-10-06 13:02:50 -05:00
..
Kconfig clk: rockchip: Add clock controller for the RK3562 2025-03-02 17:51:51 +01:00
Makefile clk: rockchip: rename gate-grf clk file 2025-05-13 20:30:15 +02:00
clk-cpu.c clk: Fix typos 2025-07-26 23:49:18 -07:00
clk-ddr.c clk: rockchip: ddr: convert from round_rate() to determine_rate() 2025-09-08 09:41:30 -04:00
clk-gate-grf.c clk: rockchip: rename gate-grf clk file 2025-05-13 20:30:15 +02:00
clk-half-divider.c clk: rockchip: half-divider: convert from round_rate() to determine_rate() 2025-09-08 09:41:25 -04:00
clk-inverter.c
clk-mmc-phase.c clk: Fix typos 2025-07-26 23:49:18 -07:00
clk-muxgrf.c
clk-pll.c clk: rockchip: pll: convert from round_rate() to determine_rate() 2025-09-08 09:41:30 -04:00
clk-px30.c
clk-rk3036.c clk: rockchip: rk3036: mark ddrphy as critical 2025-05-08 20:29:02 +02:00
clk-rk3128.c
clk-rk3188.c clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066 2025-02-26 17:52:48 +01:00
clk-rk3228.c
clk-rk3288.c clk: rockchip: introduce auxiliary GRFs 2025-05-05 22:39:24 +02:00
clk-rk3308.c
clk-rk3328.c clk: rockchip: introduce auxiliary GRFs 2025-05-05 22:39:24 +02:00
clk-rk3368.c clk: rockchip: rk3368: use clock ids for SCLK_MIPIDSI_24M 2025-09-03 14:17:54 +02:00
clk-rk3399.c
clk-rk3528.c clk: rockchip: rk3528: add slab.h header include 2025-05-15 14:49:05 +02:00
clk-rk3562.c clk: rockchip: Add clock controller for the RK3562 2025-03-02 17:51:51 +01:00
clk-rk3568.c clk: rockchip: rk3568: Add PLL rate for 132MHz 2025-07-10 13:47:36 +02:00
clk-rk3576.c I've recently moved computers (among other things) so I'm sending this from a 2025-05-30 09:15:40 -07:00
clk-rk3588.c clk: rockchip: rk3588: Add PLL rate for 1500 MHz 2025-04-10 14:28:14 +02:00
clk-rv1108.c
clk-rv1126.c clk: rockchip: introduce auxiliary GRFs 2025-05-05 22:39:24 +02:00
clk.c clk: rockchip: rename branch_muxgrf to branch_grf_mux 2025-05-13 20:30:15 +02:00
clk.h clk: Fix typos 2025-07-26 23:49:18 -07:00
gate-link.c clk: rockchip: implement linked gate clock support 2025-01-09 16:19:21 +01:00
rst-rk3528.c clk: rockchip: rk3528: Add reset lookup table 2025-02-27 20:08:25 +01:00
rst-rk3562.c clk: rockchip: Add clock controller for the RK3562 2025-03-02 17:51:51 +01:00
rst-rk3576.c
rst-rk3588.c
softrst.c