Alvin Lee a18463eff7 drm/amd/display: Update TTU properly ... [Why] We need to update TTU properly if DRAMClockChangeWatermark changes. If TTU < DRAMClockChangeWatermark, we pstate won't be allowed and we will hang in some PSR cases. [How] Update TTU if DramClockChangeWatermark value increases (only if TTU was dependent on the watermark value on the DRAMClockChangeWatermark value in the first place). Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-02-25 11:09:25 -05:00
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display_mode_vba_20.c	drm/amd/display: use odm combine for YCbCr420 timing with h_active greater than 4096	2020-01-22 16:55:28 -05:00
display_mode_vba_20.h	…
display_mode_vba_20v2.c	drm/amd/display: Update TTU properly	2020-02-25 11:09:25 -05:00
display_mode_vba_20v2.h	drm/amd/display: support "dummy pstate"	2019-07-18 14:27:26 -05:00
display_rq_dlg_calc_20.c	drm/amd/display: use true, false for bool variable in display_rq_dlg_calc_20.c	2020-01-07 11:56:34 -05:00
display_rq_dlg_calc_20.h	drm/amd/display: add some parameters to validate bandwidth functions	2019-06-22 09:34:13 -05:00
display_rq_dlg_calc_20v2.c	drm/amd/display: use true, false for bool variable in display_rq_dlg_calc_20v2.c	2020-01-07 11:56:37 -05:00
display_rq_dlg_calc_20v2.h	drm/amd/display: support "dummy pstate"	2019-07-18 14:27:26 -05:00