Dmitry Baryshkov 0e720ea8de drm/msm/dsi: do not try reading 28nm vco rate if it's not enabled ... Reading VCO rate for this PLL can cause boot stalls, if it is not enabled. Guard clk_hw_get_rate with a call to dsi_pll_28nm_clk_is_enabled(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>		2020-11-04 16:00:55 -08:00
..
dsi_pll.c	drm/msm/dsi: add support for 7nm DSI PHY/PLL	2020-09-12 09:59:58 -07:00
dsi_pll.h	drm/msm/dsi: add support for 7nm DSI PHY/PLL	2020-09-12 09:59:58 -07:00
dsi_pll_7nm.c	drm/msm/dsi_pll_7nm: restore VCO rate during restore_state	2020-11-04 08:26:25 -08:00
dsi_pll_10nm.c	drm/msm/dsi_pll_10nm: restore VCO rate during restore_state	2020-11-04 08:26:25 -08:00
dsi_pll_14nm.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284	2019-06-05 17:36:37 +02:00
dsi_pll_28nm.c	drm/msm/dsi: do not try reading 28nm vco rate if it's not enabled	2020-11-04 16:00:55 -08:00
dsi_pll_28nm_8960.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284	2019-06-05 17:36:37 +02:00