Dmitry Baryshkov 1328cb7c34 drm/msm/dsi: correct programming sequence for SM8350 / SM8450 ... According to the display-drivers, 5nm DSI PLL (v4.2, v4.3) have different boundaries for pll_clock_inverters programming. Follow the vendor code and use correct values. Fixes: 2f9ae4e395 ("drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/606947/ Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-3-1149dd8399fe@linaro.org		2024-09-02 02:53:44 +03:00
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phy	drm/msm/dsi: correct programming sequence for SM8350 / SM8450	2024-09-02 02:53:44 +03:00
dsi.c	drm/msm/dsi: simplify connector creation	2024-04-22 16:22:50 +03:00
dsi.h	drm/msm/dsi: parse vsync source from device tree	2024-06-24 19:41:05 +03:00
dsi_cfg.c	drm/msm: dsi: add support for DSI 2.8.0	2023-12-05 03:39:20 +03:00
dsi_cfg.h	drm/msm: dsi: add support for DSI 2.8.0	2023-12-05 03:39:20 +03:00
dsi_host.c	drm/msm/dsi: parse vsync source from device tree	2024-06-24 19:41:05 +03:00
dsi_manager.c	drm/msm/dsi: parse vsync source from device tree	2024-06-24 19:41:05 +03:00