Marc Zyngier ce9e40a9a5 irqchip/gic-v3-its: Limit number of per-device MSIs to the range the ITS supports ... The ITS driver blindly assumes that EventIDs are in abundant supply, to the point where it never checks how many the hardware actually supports. It turns out that some pretty esoteric integrations make it so that only a few bits are available, all the way down to a single bit. Enforce the advertised limitation at the point of allocating the device structure, and hope that the endpoint driver can deal with such limitation. Fixes: 84a6a2e7fc ("irqchip: GICv3: ITS: device allocation and configuration") Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Zenghui Yu <zenghui.yu@linux.dev> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260206154816.3582887-1-maz@kernel.org		2026-02-17 11:00:43 +01:00
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arm-gic-common.h	…
arm-gic-v3-prio.h	…
arm-gic-v3.h	irqchip/gic-v3-its: Limit number of per-device MSIs to the range the ITS supports	2026-02-17 11:00:43 +01:00
arm-gic-v4.h	…
arm-gic-v5.h	Loongarch:	2026-02-13 11:31:15 -08:00
arm-gic.h	irqchip/gic: Add missing GICH_HCR control bits	2025-11-24 14:29:11 -08:00
arm-vgic-info.h	irqchip/gic: Expose CPU interface VA to KVM	2025-11-24 14:29:11 -08:00
arm-vic.h	…
chained_irq.h	…
irq-bcm2836.h	…
irq-madera.h	…
irq-msi-lib.h	…
irq-omap-intc.h	…
irq-renesas-rzt2h.h	irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver	2025-12-15 22:44:32 +01:00
irq-renesas-rzv2h.h	…
irq-sa11x0.h	…
riscv-aplic.h	…
riscv-imsic.h	irqchip/riscv-imsic: Adjust the number of available guest irq files	2026-02-06 19:05:34 +05:30
xtensa-mx.h	…
xtensa-pic.h	…