mirror of https://github.com/torvalds/linux.git
d104e3d17f
Misc changes:
- Use str_plural() instead of open code for emitting strings.
- Use str_enabled_disabled() instead of ternary operator
- Fix emit of type resource_size_t argument for validate_region_offset()
- Typo fixup in CXL driver-api documentation
- Rename CFMWS coherency restriction defines
- Add convention doc describe dealing with x86 low memory hole and CXL
Poison Inject support series:
- Move hpa_to_spa callback to new reoot decoder ops structure
- Define a SPA to HPA callback for interleave calculation with XOR math
- Add support for SPA to DPA address translation with XOR
- Add locked variants of poison inject and clear functions
- Add inject and clear poison support by region offset
CXL access coordinates update fix series:
- A comment update for hotplug memory callback prority defines
- Add node_update_perf_attrs() for updating perf attrs on a node
- Update cxl_access_coordinates() to use the new node update function
- Remove hmat_update_target_coordinates() and related code
CXL delayed downstream port enumeration and initialization series
- Add helper to detect top of CXL device topology and remove open coding
- Add helper to delete single dport
- Add a cached copy of target_map to cxl_decoder
- Refactor decoder setup to reduce cxl_test burden
- Defer dport allocation for switch ports
- Add mock version of devm_cxl_add_dport_by_dev() for cxl_test
- Adjust the mock version of devm_cxl_switch_port_decoders_setup() due to
cxl core usage
- Setup target_map for cxl_test decoder initialization
- Change SSLBIS handler to handle single dport
- Move port register setup to when first dport appears
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEE5DAy15EJMCV1R6v9YGjFFmlTOEoFAmjdqxAACgkQYGjFFmlT
OEoayhAAqW6nPPM2XNiNigGp5oxQTt0GiblhS/PDAq+VHZaFQtrM6lvbrvqj1Gus
g49ID4SkKVq2SKZlGVk5xcPE2BEeKp4YOF6mmAqKNy6geeG0mVXf/gNbhd/8pnpm
zmbX9FdAR2x4ZimPzBZZO0vlm5NG61sVHWyz1VcU9rQUpB8shSQF3QIoKypq1MpU
G7PgN92Pc8Ztr1cI9RSFXV6p5Bd26IMt7Bi3Wub5z4rtnQAFzhtQ5oFpen6Dc4Gj
py+BwY9x25HsVCWD6oQIFvDfH5iiZfSbL62h2ttbalkqM0dFJedKmHq1rNMpsV/4
mNY2COr2uTBOB7Zht10+Q46pAAYdBTVKFIhRAEUidnCmzF8PPEAEYISo4vE5Oqih
lUJYhU8tREacLJ9jR4ro0NwgM43mESX4Aj84CV+BtPA2SyI2qsqY8xCHXyyiaLsn
GUGSbVXRbhtAWs+gM8ciERx9U/AE+yV8oABaz/zeUO5RMSB2ho6y9XD6PFHfp5Fb
w+Ud6CNkk00HR8Api38zfHJeMOR+GzsaebZgW8pOcfucC6dxS1rhUa3iN0ifLMIC
QdRSemwBjbPWJ21JwHxJCGVv/OUocziTg9H5ydZfaxOoXjIKYZcKo5ePUe4KH7bi
2tNjlA8BCycBiwaUMIMEHcIZNNm2GGddeN6TwP8QLVAevj3Hkl0=
=VYmp
-----END PGP SIGNATURE-----
Merge tag 'cxl-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl
Pull CXL updates from Dave Jiang:
"The changes include adding poison injection support, fixing CXL access
coordinates when onlining CXL memory, and delaing the enumeration of
downstream switch ports for CXL hierarchy to ensure that the CXL link
is established at the time of enumeration to address a few issues
observed on AMD and Intel platforms.
Misc changes:
- Use str_plural() instead of open code for emitting strings.
- Use str_enabled_disabled() instead of ternary operator
- Fix emit of type resource_size_t argument for
validate_region_offset()
- Typo fixup in CXL driver-api documentation
- Rename CFMWS coherency restriction defines
- Add convention doc describe dealing with x86 low memory hole
and CXL
Poison Inject support:
- Move hpa_to_spa callback to new reoot decoder ops structure
- Define a SPA to HPA callback for interleave calculation with
XOR math
- Add support for SPA to DPA address translation with XOR
- Add locked variants of poison inject and clear functions
- Add inject and clear poison support by region offset
CXL access coordinates update fix:
- A comment update for hotplug memory callback prority defines
- Add node_update_perf_attrs() for updating perf attrs on a node
- Update cxl_access_coordinates() to use the new node update function
- Remove hmat_update_target_coordinates() and related code
CXL delayed downstream port enumeration and initialization:
- Add helper to detect top of CXL device topology and remove
open coding
- Add helper to delete single dport
- Add a cached copy of target_map to cxl_decoder
- Refactor decoder setup to reduce cxl_test burden
- Defer dport allocation for switch ports
- Add mock version of devm_cxl_add_dport_by_dev() for cxl_test
- Adjust the mock version of devm_cxl_switch_port_decoders_setup()
due to cxl core usage
- Setup target_map for cxl_test decoder initialization
- Change SSLBIS handler to handle single dport
- Move port register setup to when first dport appears"
* tag 'cxl-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (25 commits)
cxl: Move port register setup to when first dport appear
cxl: Change sslbis handler to only handle single dport
cxl/test: Setup target_map for cxl_test decoder initialization
cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup()
cxl/test: Add mock version of devm_cxl_add_dport_by_dev()
cxl: Defer dport allocation for switch ports
cxl/test: Refactor decoder setup to reduce cxl_test burden
cxl: Add a cached copy of target_map to cxl_decoder
cxl: Add helper to delete dport
cxl: Add helper to detect top of CXL device topology
cxl: Documentation/driver-api/cxl: Describe the x86 Low Memory Hole solution
cxl/acpi: Rename CFMW coherency restrictions
Documentation/driver-api: Fix typo error in cxl
acpi/hmat: Remove now unused hmat_update_target_coordinates()
cxl, acpi/hmat: Update CXL access coordinates directly instead of through HMAT
drivers/base/node: Add a helper function node_update_perf_attrs()
mm/memory_hotplug: Update comment for hotplug memory callback priorities
cxl: Fix emit of type resource_size_t argument for validate_region_offset()
cxl/region: Add inject and clear poison by region offset
cxl/core: Add locked variants of the poison inject and clear funcs
...
|
||
|---|---|---|
| .. | ||
| allocation | ||
| devices | ||
| linux | ||
| platform | ||
| conventions.rst | ||
| index.rst | ||
| maturity-map.rst | ||
| theory-of-operation.rst | ||