Paul Cercueil 2b555a4b9c clk: ingenic: Add missing flag for UDC clock ... The UDC clock of the JZ4740 SoC can be gated, but the data structure representing it was missing the CGU_CLK_GATE flag to make it work. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2018-07-06 11:47:28 -07:00
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Makefile	clk: Add Ingenic jz4770 CGU driver	2018-01-18 22:05:55 +00:00
cgu.c	clk: ingenic: Support specifying "wait for clock stable" delay	2018-06-01 23:21:31 -07:00
cgu.h	docs: Fix some broken references	2018-06-15 18:10:01 -03:00
jz4740-cgu.c	clk: ingenic: Add missing flag for UDC clock	2018-07-06 11:47:28 -07:00
jz4770-cgu.c	clk: ingenic: jz4770: Add 150us delay after enabling VPU clock	2018-06-01 23:21:39 -07:00
jz4780-cgu.c	clk: ingenic: Use const pointer to clk_ops in struct	2018-01-18 22:04:36 +00:00