linux/drivers/gpu/drm/amd/display/dc/dcn30
Aurabindo Pillai 158858bf1a drm/amd/display: rework macros for DWB register access
[Why]
A hack was used to access DWB register due to difference in the register
naming convention which was not compatible with existing SR/SRI* macros.
The additional macro needed were added to dwb ip specific header file
(dcnxx_dwb.h) instead of soc resource file (dcnxx_resource.c). Due to
this pattern, BASE macro had to be redefined in dcnxx_dwb.h, which in
turn needed us to undefine them in the resource file.

[How]
Add a separate macro for DWB access to the resource files that need it
instead of defining them in DWB ip header file. This will enable us to
reuse the BASE macro defined in the resource file.

Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-11-15 13:35:15 -05:00
..
Makefile drm/amd/display: Remove FPU flags from DCN30 Makefile 2022-07-25 17:16:32 -04:00
dcn30_afmt.c
dcn30_afmt.h
dcn30_cm_common.c
dcn30_cm_common.h
dcn30_dccg.c
dcn30_dccg.h
dcn30_dio_link_encoder.c
dcn30_dio_link_encoder.h
dcn30_dio_stream_encoder.c drm/amd/display: Program ACP related register 2022-07-05 16:13:18 -04:00
dcn30_dio_stream_encoder.h drm/amd/display: Program ACP related register 2022-07-05 16:13:18 -04:00
dcn30_dpp.c drm/amd/display: Use the same cursor info across features 2022-10-10 17:32:55 -04:00
dcn30_dpp.h
dcn30_dpp_cm.c drm/amd/display: Clean up some inconsistent indenting 2022-07-28 16:05:15 -04:00
dcn30_dwb.c
dcn30_dwb.h drm/amd/display: rework macros for DWB register access 2022-11-15 13:35:15 -05:00
dcn30_dwb_cm.c
dcn30_hubbub.c
dcn30_hubbub.h
dcn30_hubp.c drm/amd/display: For stereo keep "FLIP_ANY_FRAME" 2022-08-10 15:30:06 -04:00
dcn30_hubp.h
dcn30_hwseq.c drm/amd/display: revert Disable DRR actions during state commit 2022-11-15 13:35:14 -05:00
dcn30_hwseq.h
dcn30_init.c drm/amd/display: rework recent update PHY state commit 2022-09-19 15:10:24 -04:00
dcn30_init.h
dcn30_mmhubbub.c
dcn30_mmhubbub.h drm/amd/display: rework macros for DWB register access 2022-11-15 13:35:15 -05:00
dcn30_mpc.c drm/amd/display: Clean up some inconsistent indenting 2022-07-28 16:05:15 -04:00
dcn30_mpc.h drm/amd/display: Prepare for new interfaces 2022-07-05 16:10:45 -04:00
dcn30_opp.h
dcn30_optc.c drm/amd/display: Add events log to trace OPTC lock and unlock 2022-10-24 14:36:06 -04:00
dcn30_optc.h drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code 2022-07-29 15:24:38 -04:00
dcn30_resource.c drm/amd/display: rework macros for DWB register access 2022-11-15 13:35:15 -05:00
dcn30_resource.h drm/amd/display: Add reinstate dram in the FPO logic 2022-07-25 17:17:36 -04:00
dcn30_vpg.c
dcn30_vpg.h