mirror of https://github.com/torvalds/linux.git
253 lines
8.0 KiB
Rust
253 lines
8.0 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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//! PCI interrupt infrastructure.
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use super::Device;
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use crate::{
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bindings,
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device,
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device::Bound,
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devres,
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error::to_result,
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irq::{
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self,
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IrqRequest, //
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},
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prelude::*,
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str::CStr,
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sync::aref::ARef, //
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};
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use core::ops::RangeInclusive;
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/// IRQ type flags for PCI interrupt allocation.
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#[derive(Debug, Clone, Copy)]
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pub enum IrqType {
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/// INTx interrupts.
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Intx,
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/// Message Signaled Interrupts (MSI).
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Msi,
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/// Extended Message Signaled Interrupts (MSI-X).
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MsiX,
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}
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impl IrqType {
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/// Convert to the corresponding kernel flags.
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const fn as_raw(self) -> u32 {
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match self {
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IrqType::Intx => bindings::PCI_IRQ_INTX,
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IrqType::Msi => bindings::PCI_IRQ_MSI,
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IrqType::MsiX => bindings::PCI_IRQ_MSIX,
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}
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}
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}
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/// Set of IRQ types that can be used for PCI interrupt allocation.
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#[derive(Debug, Clone, Copy, Default)]
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pub struct IrqTypes(u32);
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impl IrqTypes {
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/// Create a set containing all IRQ types (MSI-X, MSI, and INTx).
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pub const fn all() -> Self {
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Self(bindings::PCI_IRQ_ALL_TYPES)
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}
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/// Build a set of IRQ types.
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///
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/// # Examples
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///
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/// ```ignore
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/// // Create a set with only MSI and MSI-X (no INTx interrupts).
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/// let msi_only = IrqTypes::default()
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/// .with(IrqType::Msi)
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/// .with(IrqType::MsiX);
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/// ```
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pub const fn with(self, irq_type: IrqType) -> Self {
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Self(self.0 | irq_type.as_raw())
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}
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/// Get the raw flags value.
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const fn as_raw(self) -> u32 {
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self.0
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}
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}
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/// Represents an allocated IRQ vector for a specific PCI device.
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///
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/// This type ties an IRQ vector to the device it was allocated for,
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/// ensuring the vector is only used with the correct device.
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#[derive(Clone, Copy)]
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pub struct IrqVector<'a> {
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dev: &'a Device<Bound>,
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index: u32,
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}
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impl<'a> IrqVector<'a> {
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/// Creates a new [`IrqVector`] for the given device and index.
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///
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/// # Safety
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///
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/// - `index` must be a valid IRQ vector index for `dev`.
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/// - `dev` must point to a [`Device`] that has successfully allocated IRQ vectors.
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unsafe fn new(dev: &'a Device<Bound>, index: u32) -> Self {
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Self { dev, index }
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}
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/// Returns the raw vector index.
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fn index(&self) -> u32 {
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self.index
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}
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}
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impl<'a> TryInto<IrqRequest<'a>> for IrqVector<'a> {
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type Error = Error;
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fn try_into(self) -> Result<IrqRequest<'a>> {
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// SAFETY: `self.as_raw` returns a valid pointer to a `struct pci_dev`.
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let irq = unsafe { bindings::pci_irq_vector(self.dev.as_raw(), self.index()) };
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if irq < 0 {
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return Err(crate::error::Error::from_errno(irq));
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}
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// SAFETY: `irq` is guaranteed to be a valid IRQ number for `&self`.
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Ok(unsafe { IrqRequest::new(self.dev.as_ref(), irq as u32) })
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}
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}
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/// Represents an IRQ vector allocation for a PCI device.
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///
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/// This type ensures that IRQ vectors are properly allocated and freed by
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/// tying the allocation to the lifetime of this registration object.
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///
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/// # Invariants
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///
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/// The [`Device`] has successfully allocated IRQ vectors.
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struct IrqVectorRegistration {
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dev: ARef<Device>,
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}
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impl IrqVectorRegistration {
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/// Allocate and register IRQ vectors for the given PCI device.
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///
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/// Allocates IRQ vectors and registers them with devres for automatic cleanup.
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/// Returns a range of valid IRQ vectors.
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fn register<'a>(
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dev: &'a Device<Bound>,
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min_vecs: u32,
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max_vecs: u32,
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irq_types: IrqTypes,
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) -> Result<RangeInclusive<IrqVector<'a>>> {
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// SAFETY:
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// - `dev.as_raw()` is guaranteed to be a valid pointer to a `struct pci_dev`
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// by the type invariant of `Device`.
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// - `pci_alloc_irq_vectors` internally validates all other parameters
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// and returns error codes.
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let ret = unsafe {
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bindings::pci_alloc_irq_vectors(dev.as_raw(), min_vecs, max_vecs, irq_types.as_raw())
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};
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to_result(ret)?;
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let count = ret as u32;
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// SAFETY:
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// - `pci_alloc_irq_vectors` returns the number of allocated vectors on success.
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// - Vectors are 0-based, so valid indices are [0, count-1].
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// - `pci_alloc_irq_vectors` guarantees `count >= min_vecs > 0`, so both `0` and
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// `count - 1` are valid IRQ vector indices for `dev`.
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let range = unsafe { IrqVector::new(dev, 0)..=IrqVector::new(dev, count - 1) };
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// INVARIANT: The IRQ vector allocation for `dev` above was successful.
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let irq_vecs = Self { dev: dev.into() };
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devres::register(dev.as_ref(), irq_vecs, GFP_KERNEL)?;
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Ok(range)
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}
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}
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impl Drop for IrqVectorRegistration {
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fn drop(&mut self) {
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// SAFETY:
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// - By the type invariant, `self.dev.as_raw()` is a valid pointer to a `struct pci_dev`.
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// - `self.dev` has successfully allocated IRQ vectors.
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unsafe { bindings::pci_free_irq_vectors(self.dev.as_raw()) };
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}
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}
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impl Device<device::Bound> {
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/// Returns a [`kernel::irq::Registration`] for the given IRQ vector.
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pub fn request_irq<'a, T: crate::irq::Handler + 'static>(
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&'a self,
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vector: IrqVector<'a>,
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flags: irq::Flags,
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name: &'static CStr,
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handler: impl PinInit<T, Error> + 'a,
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) -> impl PinInit<irq::Registration<T>, Error> + 'a {
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pin_init::pin_init_scope(move || {
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let request = vector.try_into()?;
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Ok(irq::Registration::<T>::new(request, flags, name, handler))
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})
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}
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/// Returns a [`kernel::irq::ThreadedRegistration`] for the given IRQ vector.
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pub fn request_threaded_irq<'a, T: crate::irq::ThreadedHandler + 'static>(
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&'a self,
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vector: IrqVector<'a>,
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flags: irq::Flags,
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name: &'static CStr,
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handler: impl PinInit<T, Error> + 'a,
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) -> impl PinInit<irq::ThreadedRegistration<T>, Error> + 'a {
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pin_init::pin_init_scope(move || {
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let request = vector.try_into()?;
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Ok(irq::ThreadedRegistration::<T>::new(
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request, flags, name, handler,
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))
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})
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}
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/// Allocate IRQ vectors for this PCI device with automatic cleanup.
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///
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/// Allocates between `min_vecs` and `max_vecs` interrupt vectors for the device.
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/// The allocation will use MSI-X, MSI, or INTx interrupts based on the `irq_types`
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/// parameter and hardware capabilities. When multiple types are specified, the kernel
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/// will try them in order of preference: MSI-X first, then MSI, then INTx interrupts.
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///
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/// The allocated vectors are automatically freed when the device is unbound, using the
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/// devres (device resource management) system.
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///
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/// # Arguments
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///
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/// * `min_vecs` - Minimum number of vectors required.
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/// * `max_vecs` - Maximum number of vectors to allocate.
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/// * `irq_types` - Types of interrupts that can be used.
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///
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/// # Returns
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///
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/// Returns a range of IRQ vectors that were successfully allocated, or an error if the
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/// allocation fails or cannot meet the minimum requirement.
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///
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/// # Examples
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///
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/// ```
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/// # use kernel::{ device::Bound, pci};
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/// # fn no_run(dev: &pci::Device<Bound>) -> Result {
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/// // Allocate using any available interrupt type in the order mentioned above.
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/// let vectors = dev.alloc_irq_vectors(1, 32, pci::IrqTypes::all())?;
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///
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/// // Allocate MSI or MSI-X only (no INTx interrupts).
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/// let msi_only = pci::IrqTypes::default()
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/// .with(pci::IrqType::Msi)
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/// .with(pci::IrqType::MsiX);
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/// let vectors = dev.alloc_irq_vectors(4, 16, msi_only)?;
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/// # Ok(())
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/// # }
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/// ```
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pub fn alloc_irq_vectors(
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&self,
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min_vecs: u32,
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max_vecs: u32,
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irq_types: IrqTypes,
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) -> Result<RangeInclusive<IrqVector<'_>>> {
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IrqVectorRegistration::register(self, min_vecs, max_vecs, irq_types)
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}
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}
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