3 Commits

Author	SHA1	Message	Date
Jisheng Zhang	20802d8d47	riscv: extable: add a dedicated uaccess handler ... Inspired by commit 2e77a62cb3 ("arm64: extable: add a dedicated uaccess handler"), do similar to riscv to add a dedicated uaccess exception handler to update registers in exception context and subsequently return back into the function which faulted, so we remove the need for fixups specialized to each faulting instruction. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	2022-01-05 17:53:29 -08:00
Jisheng Zhang	2bf847db0c	riscv: extable: add `type` and `data` fields ... This is a riscv port of commit d6e2cc5647 ("arm64: extable: add `type` and `data` fields"). Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	2022-01-05 17:52:54 -08:00
Jisheng Zhang	6dd10d9166	riscv: extable: consolidate definitions ... This is a riscv port of commit 819771cc28 ("arm64: extable: consolidate definitions"). Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	2022-01-05 17:52:47 -08:00