[Why]
DML2 means that the dcn3x policy for calculating z-state support
no longer runs from validate_bandwidth.
This means we are unconditionally allowing Z8, the hardware default.
[How]
Port the policy over to DCN35, but with a few modifications:
- Don't use min_dst_y_next_start as a check for Z8/Z10 allow
- Add support for overriding the Z10 stutter period per ASIC
- Cleanup the code to make the policy assignment more clear
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
- Add missing chips for HDCP
- Add new command to disable replay timing resync
- Fix encoder disable logic
- Enable DSC Flag in MST Mode Validation
- Change the DMCUB mailbox memory location from FB to inbox
- Add disable timeout option
- Negate IPS allow and commit bits
- Enable DCN clock gating for DCN35
- Prefer currently used OTG master when acquiring free pipe
- Try to acquire a free OTG master not used in cur ctx first
- Clear dpcd_sink_ext_caps if not set
- Enable fast plane updates on DCN3.2 and above
- Add null checks for 8K60 lightup
- Refactor resource into component directory
- Fix DSC not Enabled on Direct MST Sink
- Guard against invalid RPTR/WPTR being set
- Enable CM low mem power optimization
- Fix a debugfs null pointer error
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Driver continues running whenever there is
is timeout from smu or dmcub.
It is difficult to track failure state
when dcn, dc or dmcub changes on root failure.
[HOW]
Add disable_timeout option to halt driver
whenever there is a failure in response.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
Update test link rate DPCD bit field to match spec
Enable RCO options for dcn35
Add missing dml2 init value for dcn35
Enable DCN clock gating
DCN35 Disable cm power optimization
Allow 16 max_slices for DP2 DSC
Fix OTG disable workaround logic
Enable more IPS options
Fix FRL assertion on boot
Fix missing blendTF programming
Update DP HPO MSA with colorimetry from test request
Fix handling duplicate planes on one stream
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
On boot disable domain22 force power on
decouple dmcub execution to reduce lock granularity
Enable fast update on blendTF change
Fix blend LUT programming
Program plane color setting correctly
amend HPD handler for Replay
Avoid NULL dereference of timing generator
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC v3.2.256
Summary:
* Fixes null-deref regression after
"drm/amd/display: Update OPP counter from new interface"
* Fixes display flashing when VSR and HDR enabled on dcn32
* Fixes dcn3x intermittent hangs due to FPO
* Fixes MST Multi-Stream light up on dcn35
* Fixes green screen on DCN31x when DVI and HDMI monitors attached
* Adds DML2 improvements
* Adds idle power optimization improvements
* Accommodates panels with lower nit backlight
* Updates SDP VSC colorimetry from DP test automation request
* Reverts "drm/amd/display: allow edp updates for virtual signal"
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
To enable automated testing through IGT, expose an API that is
accessible through debugfs to query current status of SubVP feature.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Intermittent reboot hangs are observed introduced by
"Improve x86 and dmub ips handshake".
[How]
Bring back the commit but fix the polling.
Avoid hanging in place forever by bounding the delay and ensure that
we still message DMCUB on IPS2 exit to notify driver idle has been
cleared.
Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Need a helper function to check idle power is allowed
so that dc doesn't access any registers that are power-gated.
[how]
Implement helper function to check idle power optimization.
Enable a hook to check if detection is allowed.
V2:
Add function hooks for set and get idle states.
Check if function hook was properly initialized.
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Nicholas Choi <nicholas.choi@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This reverts commit 1288d70208.
Causes intermittent hangs during reboot stress testing.
Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
As dc_set_power_state() no longer allocates memory, it's not necessary
to have return types and check return code as it can't fail anymore.
Change it back to `void`.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Refactor DPG test pattern logic for ODM cases
- Refactor HWSS into component folder
- Revert "drm/amd/display: Add a check for idle power optimization"
- Revert "drm/amd/display: remove duplicated edp relink to fastboot
- Update cursor limits based on SW cursor fallback limits
- Update stream mask
- Update pmfw_driver_if new structure
- Modify SMU message logs
- Don't set dpms_off for seamless boot
Known issue:
DWB (Writeback functionality) is broken.
Fix will be available in DC 3.2.256
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Rename hw_sequencer to hwseq.
Move all hwseq files to unique
folder hwss.
[how]
creating hwss repo in dc, and moved the dcnxx_hwseq.c
and .h files into corresponding new folders inside the hwss
and cleared the linkage errors by adding relative paths
in the Makefile.template.
Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Mounika Adhuri <moadhuri@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Revert commit 434cf7af49 ("drm/amd/display: Add a check for idle power optimization")
Because it cause Freesync and S4 regression
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
It's important to make sure SMU messages
are logged by default to improve debugging for
power optimization use cases.
[how]
Change logs to warnings when SMU message
returns non-success id.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC is transitioning from DML to DML2, and this commit introduces all the
required changes for some of the already available ASICs and adds the
required code infra to support new ASICs under DML2. DML2 is also a
generated code that provides better mode verification and programming
models for software/hardware, and it enables a better way to create
validation tools. This version is more like a middle step to the
complete transition to the DML2 version.
Changes since V1:
- Alex: Fix typos
Changes since V2:
- Update DC includes
Changes since V3:
- Fix 32 bit compilation issues on x86
Changes since V4:
- Avoid compilation of DML2 on some not supported 32-bit architecture
- Update commit message
Co-developed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Co-developed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC v3.2.254
* Stability fixes through null pointer checks, blackscreen fixes on
certain configurations
* Improvements for various functionality like Idle optimization, ILR, DSC, IPS
* Fixes for ILR functionality
* Trivial code cleanups
===================================================================
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Need a helper function to check idle power is allowed
so that dc doesn't access any registers that are power-gated.
[how]
Implement helper function to check idle power optimization.
Enable a hook to check if detection is allowed.
Signed-off-by: Sung Joon Kim <Sungjoon.Kim@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Clip size increase will increase viewport, which could cause us to
switch to MPC combine.
If we skip full update, we are not able to change to MPC combine in
fast update. This will cause corruption showing on the video plane.
[how]
treat clip size increase of a surface larger than 5k as a full update.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Driver needs to be compatible with PM FW that doesn't support IPS
[how]
Toggle internal control flag
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC code is reused by other OSes and so Linux return codes don't
make sense. Change dc_set_power_state() to boolean and add a wrapper
dm_set_power_state() to return a Linux error code for the memory
allocation failure.
Suggested-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
During the suspend process dc_set_power_state() will use kzalloc
to allocate memory, but this potentially fails with memory pressure.
If it fails, the suspend should be aborted.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: Harry.Wentland@amd.com
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Allow dc report maximum display clock possible at vmin
Reviewed-by: Wayne Lin <wayne.lin@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Max Tseng <max.tseng@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- Fix incorrect odm change detection logic
- Add primary pipe check when building slice table for dcn3x
- Add get primary dpp pipe resource interface
- Add missing function pointer for DCN321 resource
- Rename DisableMinDispClkODM in dc_config
- Break after finding supported vlevel for repopulate
- Update OPP counter from new interface
- Augment display clock in dc_cap structure
- Improve code style on bios_parser2
- Skip audio config for virtual signal
- Block MPO if it prevents pstate support
- Fix DP2.0 timing sync
- Improve x86 and dmub ips handshake
- Remove guaranteed viewports limitation for odm
- Add new windowed mpo odm minimal transition sequence
- Reset stream slice count for new ODM policy
- Determine fast update only before commit minimal transition state
- Remove unused mmhub_reg_offsets
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[what and why]
The logic for DisableMinDispClkODM is reversed now that odm is
disabled by default. Renaming to EnableMinDispClkODM.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This change adds a method to block mpo when it would cause us to
exit pstate support. We should block mpo by default where MPO
causes issues by preventing pstate change.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
There is a race condition between x86 and dmcub fw when attempting to exit
IPS2. Scenarios including exiting IPS2 before IPS2 has been entered. This
can cause unexpected hang when DMCUB attempt to exit while PMFW still
tries to enter IPS2.
[How]
A new design has been introduced to remove race conditions and improve the
handshake between x86 and DMCUB. An AON scratch register is borrowed from
PMFW to determine whether DMCUB has committed to IPS entry or not.
In the case when dmcub has committed IPS entry, x86 must poll until an exit
event occurred either from DMCUB(IPS1) or PMFW(IPS2). x86 will wait
upperbound of evaluation and IPS entry time to ensure IPS2 exit event has
been sent to PMFW.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- Use optc32 instead of optc30 in DC
- Optimize OLED T7 delay
- Multiple fixes for MST, register mas, and others
- Update driver and IPS interop
- Improve z8 watermark mask
- DCN35 updates
- Enable replay for DCN35
- Temporarily disable clock gating
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add a config option to disable odm dispclk optimization for debug
purpose.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Add new logs to be used by the AutoDPMTest
- Enclose AutoDPMTest logs in settings
- Add logging definition
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Ethan Bitnun <etbitnun@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- DCN315 fixes
- DCN31 fixes
- DPIA fixes
- Dump the pipe topology when it updates
- Misc code cleanups
- New debugfs interface to query the current ODM combine configuration
- ODM fixes
- Potential deadlock while waiting for MPC idle fix
- Support for windowed MPO ODM
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
For DPIA we should have preferred DIG assignment based on DPIA selected
as per the ASIC design.
Reviewed-by: George Shen <george.shen@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Ensure FS is enabled before sending request to DMUB for FS changes
- Add check for PMFW hard min request complete
- Save addr update in scratch before flip
- Fix static screen detection setting
- Write flip addr to scratch reg for subvp
- set minimum of VBlank_nom
- Correct unit conversion for vstartup
- Roll back unit correction
- Enable runtime register offset init for DCN32 DMUB
- Refactor edp power control
- PQ regamma end point
- PQ tail accuracy
- Expose mall capability
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
To organize the edp power control a bit:
1. add flag in dc_link to indicate dc to skip all implicit eDP power control.
2. add edp_set_panel_power link service for DM to call.
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Improve power saving feature
- Clean up for code clarity
- Fix crashing bug
- Fix pipe allocation for older ASIC
- Fix for gamut remap
- Fix 8K 60Hz display in test cases
- Fix bug in clock gating
- Improve DP2 compliance
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Certain retimer requires workarounds in order to correctly output test patterns.
[HOW]
Add vendor-specific aux sequences to program retimer's TX and pattern generator
when specific compliance test patterns are requested by sink.
Note: SQ128 w/a in DPMF mode only works in one flip orientation currently
Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Fix a regression in blank pixel data caused by coding mistake
- Fix a bug when searching for insert_above_mpcc
- Update add plane to context logic with a new algorithm
- Adjust visual confirm dpp height offset to be 1/240 of v addressable
- Add interface to enable DPIA trace
- Support plane clip with zero recout size
- Blocking invalid 420 modes on HDMI TMDS for DCN31 and DCN314
- Make mpc32 functions available to future DCNs
- Change HDCP update sequence for DM
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Martin Leung <martin.leung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
We need certain conditions for replay to be enabled, so create an
interface in DM to enable/disable replay.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
Add new interface for notifying OS of cursor support changes
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
In some instances, the GPU is transmitting repeated frame to the sink
without any updates or changes in the content. These repeat transmission
are wasteful, resulting in power draw in different aspects of the system
1. DCN is fetching the frame of data from DF/UMC/DRAM. This memory traffic
prevents power down of parts of this HW path.
2. GPU is transmitting pixel data to the display through the main link of
the DisplayPort interface. This prevents power down of both the Source
transmitter (TX) and the Sink receiver (RX)
The concepts of utilizing replay is similar to PSR, but there is a benefit of:
Source and Sink remaining synchronized which allows for
- lower latency when switching from replay to live frames
- enable the possibility of more use cases
- easy control of the sink's refresh rate during replay
Due to Source and Sink remaining timing synchronized, Replay can be activated
in more UI scenarios.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Fix underflow issue on 175hz timing
- Add interface to modify DMUB panel power options
- Remove check for default eDP panel_mode
- Add new sequence for 4-lane HBR3 on vendor specific retimers
- Update DPG test pattern programming
- Correct unit conversion for vstartup
- Exit idle optimizations before attempt to access PHY
- Refactor recout calculation with a more generic formula
- Read down-spread percentage from lut to adjust dprefclk.
- Don't apply FIFO resync W/A if rdivider = 0
- Prevent invalid pipe connections
- Rearrange dmub_cmd defs order
- Add VESA SCR case for default aux backlight
- Guard DCN31 PHYD32CLK logic against chip family
- Correct grammar mistakes
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Update 128b/132b downspread factor to 0.3%
- Add helpers to get DMUB FW boot options
- Initialize necessary uninitialized variables
- Add stream overhead in BW calculations for 128b/132b
- Add link encoding to timing BW calculation parameters
- Prevent vtotal from being set to 0
- Fix race condition when turning off an output alone
- Keep PHY active for DP displays on DCN31
- Fix ASIC check in aux timeout workaround
- ABM pause toggle
- Add missing triggers for full updates
- Disable MPC split by default on special asic
- Add additional refresh rate conditions for SubVP cases
- Fix DP2 link training failure with RCO
- Reenable all root clock gating options
- Cache backlight_millinits in link structure and setting brightness accordingly
- Refine to decide the verified link setting
- Update SW cursor fallback for subvp high refresh
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Allow ABM states to be transferred across display
adapters for smooth display transitions.
[how]
We call DMUB to pause and get ABM states. We
transfer data to other gpu, and deliver data and
ask ABM to un-pause.
Reviewed-by: Harry Vanzylldejong <harry.vanzylldejong@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Reza Amini <reza.amini@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
There certain cases where the timing BW is dependent on the type of link
encoding in use. Thus to calculate the correct BW required for a given
timing, the link encoding should be added as a parameter.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Current BW calculations do not account for the additional padding added
for uncompressed pixel-to-symbol packing.
This results in X.Y being too low for 128b/132b SST streams in certain
scenarios. If X.Y is too low, end user can observe image corruption.
[How]
Add function to calculate stream overhead to timing BW calculation for
128b/132b SST cases.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Setup stream encoder before link enable for TMDS
- Use is_dig_enable function instead of dcn10 hardcode
- Re-add aux intercept disable delay generically for 2+ LTTPRs
- Add polling method to handle MST reply packet
- Remove unused function
- Improve the include of header file
- Add missing static
- Hardcode vco_freq for dcn316
- Reduce stack size
- Skip enabling DMCUB when using emulation
- Check TG is non-null before checking if enabled
- Update scaler recout data for visual confirm
- Skip querying caps when DMCUB emulation is in use
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Need to save the cached backlight level so that display lights up using
appropriate brightness level instead of the default brightness when
waking up from s0i3.
[How]
Adding a backlight level cache in link structure. Also instead on
calling set_default_brightness_aux, check if cached values exists.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Nicholas Susanto <nicholas.susanto@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Issue not display generic, required for multiple 2+ LTTPR link configurations.
[HOW]
Revert monitor patch change and remove delay for single LTTPR case
Reviewed-by: George Shen <george.shen@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Quash 175 kernel-doc warnings in dc.h by unmarking 2 struct
comments as containing kernel-doc notation and by spelling one
struct field correctly in a kernel-doc comment.
Fixes: 1682bd1a6b ("drm/amd/display: Expand kernel doc for DC")
Fixes: ea76895ffa ("drm/amd/display: Document pipe split policy")
Fixes: f6ae69f49f ("drm/amd/display: Include surface of unaffected streams")
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com>
Cc: dri-devel@lists.freedesktop.org
This version brings along the following:
- Improve debugging mechanism for Gaming FAMS
- Add monitor specific edid quirks
- Fixes for Phantom pipe
- Fixes for Shapper LUT
- Clean up asserts
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
To enable FAMS even during gaming sessions.
[HOW]
By leveraging a new dc.debug parameter.
Reviewed-by: Felipe Clark <felipe.clark@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Gianna Binder <gianna.binder@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- We want to limit the new fast update path to address and gamma updates
only.
- Add a check in dc_update_planes_and_stream to only take the new fast
update path if we only have the specific fast updates defined.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
This display doesn't properly indicate link loss through DPCD bits such
as CR_DONE / CHANNEL_EQ_DONE / SYMBOL_LOCKED / INTERLANE_ALIGN_DONE,
which all remain set.
In addition, DPCD200Eh doesn't match the value of DPCD204h in all cases.
For these reasons, we can miss re-training the link, since we don't
properly detect link loss with this display.
[Why]
Add display-specific workaround to read DPCD204h, so that we can detect
link loss based on 128b132b-specific status bits in this register.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Ilya Bakoulin <ilya.bakoulin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- DCN314 fixes
- DCN32x fixes
- New fast update sequence enablement
- DC mode clock switching enablement for DCN32x
- DP link loss fix
- New debugfs entry to set MST link settings
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
- DC mode clock switch interface was previously only executed
for DCN303. Enable it for DCN32x so that the interface is called
correctly
- Assign function pointers for DCN32x that are used in the dc mode
interface
- Update the dc mode interface to work generically for each ASIC
- In update_clocks, make sure to consider softmax if we're in DC mode
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Improvement on eDP
- PSR bug fixes
- SubVP bug fixes
- Improvements on pipe handling to address potential issues
- Freesync bug fix
- DPIA bug fix
- Fix multi-display issues
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Why:
Some EDIDs report a minimum refresh rate lower than what HW can support
How:
Add a check to calculate minimum supported refresh rate with current timing
and use that as the minimum if a lower one is passed in
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Austin Zheng <austin.zheng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Why:
Log DP2 data to be used for debugging purposes
How:
Check the reported link rate of the DP connection and
translate it to the DP version.
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Austin Zheng <austin.zheng@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Why:
Limit maximum clock speeds to DC mode limits for DC mode systems
How:
Store DC mode limits when individual clocks are initialized and
cap the values when building the clock table
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Austin Zheng <austin.zheng@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Refactor HW sequencer to use a build / execute sequence
- Also move gamma updates to become fast
v2: squash in build fix ("drm/amd/display: Fix guarding of 'if (dc->debug.visual_confirm)'")
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Improve the message printed
- Disable dcn315 pixel rate crb when scaling
- Update SR watermarks for DCN314
- Fix dcn315 pixel rate crb scaling check
- Reset CRTC State Before Restore from S2idle
- Have Payload Properly Created After Resume
- Trigger DIO FIFO resync on commit streams
- Revert vblank change that causes null pointer crash
- Fix possible underflow for displays with large vblank
- Apply 60us prefetch for DCFCLK <= 300Mhz
- Update correct DCN314 register header
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
The DMUB diagnostic data was not printed out correctly.
[How]
Print the DMUB diagnostic data line by line.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Cruise Hung <cruise.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why && How]
We would like to have visual confirm color support for MCLK switch.
1. Set visual confirm color to yellow: Vblank MCLK switch.
2. Set visual confirm color to cyan: FPO + Vblank MCLK
switch.
3. Set visual confirm color to pink: Vactive MCLK switch.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Some 1920x1080@60hz displays have VBLANK time > 600us which we
still want to accept for FPO + Vactive configs based on testing
- Increase max VBLANK time to 1000us to allow these configs
for FPO + Vactive
- Increase minimum vactive switch margin for FPO + Vactive to 200us
- Based on testing, 1920x1080@120hz can have a switch margin
of ~160us which requires significantly longer FPO stretch
margin (5ms) which we don't want to accept for now
- Also move margins into debug option
Reviewed-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Update clocks is skipped in the GPU overclock sequence
- However, we still need to update DISPCLK, DPPCLK, and DTBCLK
because the GPU overclock sequence could temporarily disable
ODM 2:1 combine because we disable all planes in the sequence
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Block SubVP on displays that have pixclk > 1800Mhz
- Block SubVP high refresh when VRR active fixed
- Enforce 60us prefetch for 200Mhz DCFCLK modes
- Check Vactive for VRR active for FPO + Vactive
- Add symclk workaround during disable link output
- Show the DCN/DCE version in the log
- Add additional pstate registers to HW state query
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- FW Release 0.0.165.0
- Add w/a to disable DP dual mode on certain ports
- Revert "Update scaler recout data for visual confirm"
- Filter out invalid bits in pipe_fuses
- Adding debug option to override Z8 watermark values
- Change default Z8 watermark values
- Workaround wrong HDR colorimetry with some receivers
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Certain ports on DCN3.2 configs do not properly populate the BIOS
info table flag to indicate DP dual mode is unsupported.
[How]
Add a workaround to disable DP dual mode on the ports with the missing
BIOS info table flag.
Reviewed-by: Michael Strauss <Michael.Strauss@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
Adding debug options to override Z8 watermark values for testing purposes.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Leo Chen <sancchen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Some scalers do not pick up color space updates unless the DP link
is disabled/re-enabled which can result in incorrect/washed out
HDR colors in some cases.
[How]
Call set_dpms_on to disable the link, re-train and re-enable with the
updated output color space.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This DC version brings along:
- Improvements in the SubVP feature
- Keep disable aux-i delay as 0
- Add p-state debugging and improvements
- Fix in secure display context creation
- add option to use custom backlight caps
- Lowering min Z8 residency time
- Restore rptr/wptr for DMCUB as workaround
- Update FW feature caps struct
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
- We want to disable SubVP if Graphics Error Correction/Correcting Code
(GECC) is enabled.
- After reading feature caps from DMCUB during init, use the GECC
enable/disable info to determine if SubVP can be enabled or not.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Add debug option to enable SubVP for high refresh rate displays
- For now limit the enabled modes based on a table in debug options
- Currently disabled by default
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Flickering and underflow was observed when testing extended
blank on dcn314.
[What]
Vstartup is contrainted by vblank_nom, so adjusting it to include
non-adjusted vtotal in its calculation during freesync video
means that Vstartup is not changed when vtotal changes.
This fixed the flickering + underflow.
dc_extended_blank_supported function was removed
because extended blank is only relevant to when
zstate is supported. The increased vtotal during
freesync can be passed to dml regardless of whether
extended blank is supported or not, so this function is
not needed.
Updates were made recently in dml to the calculation of
min_dst_y_next_start. Dml input for dcn314 will now
always use the newer calculation for min_dst_y_next_start.
Dml input for older dcn versions remains untouched.
The variable optimized_min_dst_y_next_start
is replaced everywhere with min_dst_y_next_start,
and the updated dml allows min_dst_y_next_start to
increase to an optimized value during freesync video,
then return to default when freesync is disengaged.
Also removed registry key for controlling
extended blank feature.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Enable SubVP on PSR panels now that we have FW support
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
32ms delay was added to resolve issue with a specific sink, however this same
delay also introduces erroneous link training failures with certain sink
devices.
[HOW]
Only apply the 32ms delay for offending devices instead of globally.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This DC version brings along:
- FW Release 0.0.162.0
- Enable FPO+Vactivate
- Support for VESA SCR
- Refactor DMUB commands
- Fixes in secure display, modeset, memleak and more
- Picked up missed patches in history
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Three functions in the amdgpu display driver cause -Wmissing-prototype
warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:1858:6: error: no previous prototype for 'is_timing_changed' [-Werror=missing-prototypes]
is_timing_changed() is actually meant to be a global symbol, but needs
a proper name and prototype.
Fixes: 17ce8a6907 ("drm/amd/display: Add dsc pre-validation in atomic check")
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
When link training during engine recovery, ASSR might fail causing panel
mode to be reset to default. This should not happen for eDP as it
will prevent the panel from turning back on.
[How]
Added dp_panel_mode to struct dc_link to remember previously applied
panel mode. Do not reset panel mode to default while performing link
training if previously used panel mode = eDP.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Michael Mityushkin <michael.mityushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This DC version brings along:
- FW Release 0.0.161.0
- Improvements on FPO/FAMS
- Correction to DML calculation
- Fix to multiple clock related issues
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
New sequence for transparent mode DP1.x link training was provided by LTTPR
vendor
[HOW]
Implement new FIXED_VS sequence, increase LT retry count to minimize
any potential intermittent lightup failures
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- On init if a display is connected, we need to maintain the DISPCLK
frequency
- Even though DPG_EN=1, the display still requires the correct
timing or it could cause audio corruption (if DISPCLK freq
is reduced)
- Read the current DISPCLK freq and request the same value to ensure
the timing is valid and unchanged
- However, add option to do a full pipe power down (including link)
which will also avoid audio related issues
- Disabled for the time being on dcn32
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- When determining FPO support, include FPO + VActive support
- Support FPO + VActive if one display meets regular requirements
for FPO and the second display is able to switch in VACTIVE with
a given amount of margin
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This DC version brings along:
- Enable FPO optimization
- Support for 6.75 GBps link rate
- Fixes to underflow, black screen and more
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
The 6.75 GBps link rate is part of the new eDP specification
version 1.5 is going to be supported in the future.
Since this standard is very new and there are no existing 6.75 GBps
panels on the market yet, we should put a condition in the driver
on enabling this feature until we can validate it with real hardware.
[How]
- Add boolean flag support_eDP1_5 in struct dc_debug_options.
- Enable the 6.75 link rate in reduce_link_rate(...) only when
the flag is true.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Artem Grishin <Artem.Grishin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- On high refresh rate DRR displays that support VBLANK naturally,
UCLK could be idling at DPM1 instead of DPM0 since it doesn't use
FPO
- To achieve DPM0, enable FPO on these configs even though it can
support P-State without FPO
- Default disable for now, have debug option to enable
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This DC version brings along:
- Power down eDP if eDP not present
- Set MPC_SPLIT_DYNAMIC for DCN10 and DCN301
- Initialize link_srv in virtual env
- Code cleanup and alignment
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
In order to follow the new protocol of calling link functions
[HOW]
Add the function pointer to the link_srv
Reviewed-by: Kshitij Bhardwaj <kshitij.bhardwaj1@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
When calling the dc_link_bw_kbps_from_raw_frl_link_rate_data from
amdgpu_dm, GCC highlighted the following issue:
In function ‘get_conv_frl_bw’:
error: passing argument 1 of
‘dc_link_bw_kbps_from_raw_frl_link_rate_data’ discards ‘const’ qualifier
from pointer target type [-Werror=discarded-qualifiers]
997 | aconnector->dc_link->dc,
This commit fix this issue by making DC a constant variable since we
only use it to invoke the function
bw_kbps_from_raw_frl_link_rate_data().
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- FW Release 0.0.158.0
- Fixes to HDCP, DP MST and more
- Improvements on USB4 links and more
- Code re-architecture on link.h
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
All dc subcomponents should call another dc component via function pointers
stored in a component structure. This is part of dc coding convention since
the beginning. The reason behind this is to improve encapsulation and
polymorphism. The function contract is extracted into a single link service
structure defined in link.h header file and implemented only in link_factory.c instead
of spreading across multiple files in link component file structure.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The fields blends_with_above and blends_with_below of struct
dc_plane_cap (defined in dc/dc.h) are boolean and set to true by
default. All instances of a dc_plane_cap maintain the default values of
both. Also, there is only one if statement that checks those fields and
there would be the same effect if it was deleted (assuming that those
fields are always going to be true).
For this reason, considering both fields as legacy ones, this commit
removes them and the aforementioned if statement.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: David Tadokoro <davidbtadokoro@usp.br>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
In this new version there are two major changes:
1) Transitioning to the new DC commit sequence
There is an extended effort to migrate to the new DC commit sequence
that better adheres to the DCN hardware constraints. Most of the code
was upstreamed already but not connected to amdgpu_dm, and in this new
DC version, our DM finally started to use it for all ASICs. This should
improve stability and enable us to improve how pipe split works.
2) Drop old CONFIG_DRM_AMD_DC_DCN in favor of new CONFIG_DRM_AMD_DC_FP
For historical reasons, we created CONFIG_DRM_AMD_DC_DCN to isolate
FPU-related code to only be used for DCN. Over the years, we lost
control over this guard, and it was spread in multiple areas. In this
new DC version, there is an effort to remove all unnecessary
CONFIG_DRM_AMD_DC_DCN and replace the others for CONFIG_DRM_AMD_DC_FP,
which better describes which type of code this guard is intended for.
Finally, this version brings along the following:
- Enable HostVM based on rIOMMU active
- Keep PHY active for dp confi
- Improves Z8
- Update clock table
- Code and directives clean up
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
There are two functions responsible for handling the DC commit state:
dc_commit_state and dc_commit_streams. Both have the same goal, but
dc_commit_streams surpess dc_commit_state in terms of completeness. For
this reason, maintaining these two functions makes maintainability
unnecessarily complicated. This commit replaces the old dc_commit_state
in favor of dc_commit_streams, and removes the old dc_commit_state.
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
The only reason we have the DCN config is for
floating point support. Rename it to make that
clear and (hopefully) avoid misuse of the config
in the future.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
link component should only have one interface serving dc.
[how]
We are moving dc_link functions exposed to DM to dc_link_exports
and unify link component interface in link.h with function pointer
to match the style of other dc component. This is the third step to move
dc_link functions under protocols folder to dc_link_exports.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
link component should only have one interface serving dc.
[how]
We are moving dc_link functions exposed to DM to dc_link_exports
and unify link component interface in link.h with function pointer
to match the style of other dc component. This is the first step to move
dc_link functions under accessories folder to dc_link_exports.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
There is no reason we still need a config option for this.
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Allows finer control and tuning for debug and profiling.
[How]
Add the debug option into DC. The default remains the same as before
for now.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- Correct way to find OPP index
- Unify DC logging for BW Alloc
- Add height granularity limitation for dsc slice height calculation
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- Correct DML calculation
- Extend Freesync over Pcon support
- Fixes in pstate hang and more
- Code cleanup for dc_link.h and dc_link.c
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Remove the need to include dc_link.h separately. dc.h should contain
everything needed on DM side.
[How]
Merge dc_link.h into dc.h and dc_types.h so DM only needs to include
dc.h to use all link public functions.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
- If for any reason PMFW fails to set the expected (or valid)
DISPCLK WDIVIDER, then DAL will program DENTIST DISPCLK
WDIVIDER to correct for this issue
Reviewed-by: Samson Tam <Samson.Tam@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
Temporarily disable SubVP+DRR since Xorg has an architectural limitation
where freesync will not work in a multi monitor configuration. SubVP+DRR
requires that freesync be working.
Whether OS has variable refresh setting enabled or not, the state on
the crtc remains same unless an application requests VRR. Due to this,
there is no way to know whether freesync will actually work or not
while we are on the desktop from the kernel's perspective.
If userspace does not have a limitation with multi-display freesync (for
example wayland), then this feature can be enabled by adding a
dcfeaturemask option to amdgpu on the kernel cmdline like:
amdgpu.dcfeaturemask=0x200
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- Move domain power control to DMCUB for DCN314
- Enable P-state validation check for DCN314
- Add support for multiple overlay planes
- Fixes in prefetch, k1 k2 divider programming and more
- Code cleanup
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Link is a subcomponent in dc. DM should be aware of dc link structure
as one of the abstracted objects maintained by dc. However it should
have no idea of the existence of a link component in dc dedicated to
maintain the states of dc link structure. As such we are moving link interfaces
out of dc_link.h and directly added to dc.h. We are grandually fading out
the explicit inclusion of dc_link header and eventually delete it.
On dc side, since link is a subcomponent behind dc interfaces, it is not
a good idea to implement dc interfaces in each individual subcomponent
of link which is already a subcomponent of dc. So we are decoupling it
by implementing a dc_link_exports in dc. This file will be a thin
translation layer that breaks the dependency so link is able to make
interface changes without breaking DM.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
A recent change was made to implement temporary workaround due DRM
update in MST interfaces. The workaround is added into our generic
deallocation MST sequence.
This ticket is to extract this temporary workaround into its own function so
it is differentiated from our generic sequence.
Reviewed-by: Jerry Zuo <Jerry.Zuo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- FW 0.0.153.0
- Code re-organize for dc_link.c
- Bug fixes on rotation, DRR and more
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why && How]
Add support to read manufacturer OUI
and device id from HDMI SCDC.
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- fix linux dp link lost handled only one time
- Reset DMUB mailbox SW state after HW reset
- Unassign does_plane_fit_in_mall function from dcn3.2
- Add Function delaration in dc_link
- Fix crash when connecting 2 displays with video playback
- Adjust downscaling limits for dcn314
- fix FCLK pstate change underflow
- Fix only one ABM pipe enabled under ODM combined case
- Add missing brackets in calculation
- Correct bw_params population
- Fix Z8 support configurations
- Add Debug Log for MST and PCON
- fix MALL size hardcoded for DCN321
- add rc_params_override option in dc_dsc_config
- Enable Freesync over PCon
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Fix timing not changning when freesync video is enabled
- avoid disable otg when dig was disabled
- Properly reuse completion structure
- Pass DSC slice height to PSR FW
- merge dc_link_dp into dc_link
- move dp cts functions from dc_link_dp to link_dp_cts
- move dp irq handler functions from dc_link_dp to link_dp_irq_handler
- Enable AdaptiveSync in DC interface
- adjust MALL size available for DCN32 and DCN321
- Set init freq for DCFCLK DS
- Use |= when assigning wm_optimized_required
- move eDP panel control logic to link_edp_panel_control
- create accessories, hwss and protocols sub folders in link
- Disable SubVP for PSR panels
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Start enabling AdaptiveSync feature on Linux environment.
[how]
Adding AdaptiveSync support in DC layer
- building AdaptiveSync info_packets
- adjusting the v_startup parameter
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- [FW Promotion] Release 0.0.150.0
- Correcting prefetch mode for fast validate
- Set hvm_enabled flag for S/G mode
- set allow_freesync parameter in DM
- Revert "ignore msa parameter only if freesync is enabled"
- Allow idle optimization after turning off all pipes
- Guard Freesync HDMI parsing with dc_lock
- Speed up DML fast_validate path
- Disable MALL SS and messages for PSR supported configs
- force connector state when bpc changes during compliance
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Revert patches that caused regressions associated with audio and an
old change that checks the DCN version.
- Refactor DDC and HDP.
- Move DPIA and DPCD logic to new files.
- Updates to DMUB.
- Optimization and bug fixes for SUBVP/DRR.
- Drop legacy code.
Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
keep dig_fifo enable for test pattern generation.
Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
-Fix array index out of bound error
-Speed up DML fast vadlaite
-Implement multiple secure display
-MST HDCP for multiple display
-Add DPIA notification
-Add support for three new square pattern variant
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
Add debug bit to disable unbounded requesting.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
It's currently tied to Z10 support, and is required for Z10, but
we can still support Z10 display off without PSR.
We currently need to skip the PSR CRTC disable to prevent stuttering
and underflow from occuring during PSR-SU.
[How]
Add a debug option to allow specifying this separately.
Reviewed-by: Robin Chen <robin.chen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
-Program output transfer function when required
-Fix arthmetic errror in MALL size caluclations for subvp
-DCC Meta pitch used for MALL allocation
-Debugfs entry to tell if connector is DPIA link
-Use largest vready_offset in pipe group
-Fixes race condition in DPIA Aux transfer
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
-Add configuration 2 for ABM 2.3/2.4.
-Add margin for HUBP for SubVp + DRR.
-Fix no display after resume from WB/CB.
-Limit HW cursor size to be less than 64 x 64 bytes when the stream is >= 4K.
-Lower watermarks for enter/enter+exit latency.
-Update support types for DCN314 to include z8 only and z8_z10 only state.
-Add new value for soc bounding box and dummy pstate.
-Override fclk chang latency when calculating prefetch schedule for subvp with low uclk.
-Add check for DET fetch latency for dcn32.
-Add check if PSR enabled when entering MALL.
-Use base MALL allocation size calculations off vewport height.
-Add YCBCR2020 to CSC matrix.
-Implement DP-Tx portion to interact with DPIA.
-Add debug option for increasing phantom lines.
-Fix phantom plane/stream retain after fail validation.
-Fix display corruption with VSR enable.
-Set valid divider value for virtual and FRL/DP2.
-Add new num clk levels struct for max mclk index.
-Fix check for phantom BPP.
-Fix rotated cursor offset calculation.
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Add debug option for increasing number of phantom lines
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Even if we block Z9 based on crossover threshold it's possible to
allow for Z8.
[How]
There's support for this on DCN314, so update the support types to
include a z8 only and z8_z10 only state.
Update the decide_zstate_support function to allow for specifying
these modes based on the Z8 threshold.
DCN31 has z-state disabled, but still update the legacy code to
map z8_only = disallow and z10_z8_only = z10_only to keep the support
the same.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Add margin for HUBP "jitter" for SubVp + DRR case
- Also do a min transition even if MPO is added on a
non SubVP pipe (i.e. added on DRR pipe for SubVP + DRR)
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fix these kernel-doc complaints:
drivers/gpu/drm/amd/display/dc/dc.h:505: warning: cannot understand function prototype: 'struct dc_clocks '
dc.h:472: warning: Enum value 'MPC_SPLIT_AVOID' not described in enum 'pipe_split_policy'
dc.h:472: warning: Enum value 'MPC_SPLIT_AVOID_MULT_DISP' not described in enum 'pipe_split_policy'
dc.h:532: warning: Incorrect use of kernel-doc format: * @fw_based_mclk_switching
Fixes: ea76895ffa ("drm/amd/display: Document pipe split policy")
Fixes: 1682bd1a6b ("drm/amd/display: Expand kernel doc for DC")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Cc: David Airlie <airlied@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC version 3.2.212 brings along the following fixes:
- Fix DPIA AUX timeout issue
- Add HUBP surface flip interrupt handler
- Fix dpms_off issue when disabling bios mode
- Update SubVP Visual Confirm
- Program pipes for ODM when removing planes
- Use min transition for all SubVP plane add/remove
- Support parsing VRAM info v3.0 from VBIOS
- Enable dchub request limit for NV32
- Workaround to increase phantom pipe vactive in pipesplit
- Fix dcn3.1x mode validation on high bandwidth config
- Check context constructed for pipe split flags after pipesplit
- Align phantom pipe dst/src scaling with main for subvp
- Fix calculation for cursor CAB allocation
- Fix unbounded requesting for high pixel rate modes on dcn315
- Revert Disable DRR actions during state commit
- Fix array index out of bound error in bios parser
- Fix optc2_configure warning on dcn314
- Fix Subvp phantom pipe transition
- Fix prefetch calculations for dcn32
- Use uclk pstate latency for fw assisted mclk validation dcn32
- Set max for prefetch lines on dcn32
- Rework macros for DWB register access
- Adjust DP 8b10b LT exit behavior
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
HW recommend we enable this for better DF QoS for DCN 3.2.x
[how]
Add interfaces to hubbub to program register
Add initialization as part of init_hw
Add default settings for DCN 3.2.x
Add registry override for debug/tuning
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Jun Lei <jun.lei@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC version 3.2.211 brings along the following fixes:
- Wait for VBLANK during pipe programming
- Adding HDMI SCDC DEVICE_ID define
- Cursor update refactor: PSR-SU support condition
- Update 709 gamma to 2.222 as stated in the standerd
- Consider dp cable id only when data is non zero
- Waiting for 1 frame to fix the flash issue on PSR1
- Update SR watermarks for DCN314
- Allow tuning DCN314 bounding box
- Zeromem mypipe heap struct before using it
- Use min transition for SubVP into MPO
- Disable phantom OTG after enable for plane disable
- Disable DRR actions during state commit
- Fix fallback issues for DP LL 1.4a tests
- Fix FCLK deviation and tool compile issues
- Fix reg timeout in enc314_enable_fifo
- Fix gpio port mapping issue
- Only update link settings after successful MST link train
- Enforce minimum prefetch time for low memclk on DCN32
- Set correct EOTF and Gamut flag in VRR info
- Add margin for max vblank time for SubVP + DRR
- Populate DP2.0 output type for DML pipe
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Reviewed-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Incorporate FW delays as port of max VTOTAL calculated for
SubVP + DRR cases (since it is part of the microschedule).
- Also add margin for the max VTOTAL possible for SubVP + DRR cases.
- Due to rounding errors in FW (integer arithmetic), the microschedule
calculation can get pushed to the next frame (incorrectly) in cases
where we use the max VTOTAL possible to complete the MCLK switch.
- When the rounding error occurs, we are only off by 1-2 lines,
use 40us margin which is working consistently.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY?]
Data return times when using lowest memclk can be <= 60us, which can cause
underflow on high bandwidth displays with a workload.
[HOW?]
Enforce a minimum prefetch time during validation for low memclk modes.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC version 3.2.210 brings along the following:
- Investigate tool reported FCLK P-state deviations
- Fix null pointer issues found in emulation
- Add DSC delay factor workaround
- Round up DST_after_scaler to nearest int
- Use forced DSC bpp in DML
- Fix DCN32 DSC delay calculation
- Add a debug option HBR2CP2520 over TPS4
- Stop waiting for vblank during pipe programming
- Modify checks to enable TPS3 pattern when required
- Remove rate check from pixel rate divider update
- Check validation passed after applying pipe split changes
- Update DML formula
- Don't enable ODM + MPO
- Include virtual signal to set k1 and k2 values
- Reinit DPG when exiting dynamic ODM
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Certain 4K high refresh rate modes requiring DSC are exhibiting top
of screen underflow corruption. Increasing the DSC delay by a factor
of 6 percent stops the underflow for most use cases.
[How]
Multiply DSC delay requirement in DML by a factor.
Add debug option to make this DSC delay factor configurable.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How] There are cases when we may need to override the hardcoded
TPS4 test pattern. Added parameters and config option to be able to
allow this.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Leo Chen <sancchen@amd.com>
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The file dc.c has multiple comments that do not follow the kernel-doc or
are made in a distracting way. This commit alleviates part of this issue
by reorganizing some comments inside the dc file.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC version 3.2.209 brings along the following:
* Improve color manipulation
* Add corrections to DML and some flag configuration
* Updates for DCN32x
* Expand kernel-doc
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit adds extra documentation for elements related to FAMs.
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Reviewed-by: Aurabindo Pillai <Aurabindo.Pillai@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
We split out PSR config from "global" to "per-panel" config settings.
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Reviewed-by: Robin Chen <robin.chen@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC stream can be seen as a representation of the DCN backend or the data
struct that represents the center of the display pipeline. The front end
(i.e., planes) is connected to the DC stream, and in its turn, streams
are connected to the DC link. Due to this dynamic, DC must handle the
following scenarios:
1. A stream is removed;
2. A new stream is created;
3. An unchanged stream had some updates on its planes.
These combinations require that the new stream data struct become
updated and has a valid global state. For handling multiple corner cases
associated with stream operations, this commit introduces a function
dedicated to manipulating stream changes and invokes the state
validation function after that.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Co-developed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The commit stream function does not include surfaces of unaffected
streams, which may lead to some blank screens during mode change in some
edge cases. This commit adds surfaces of unaffected streams followed by
kernel-doc for documenting some of the fields that participate in this
change.
v2: squash in kerneldoc warning fix (Alex)
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Co-developed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC adds an instance of DML (which contains VBA) to each context, and
multiple threads might write back to the global VBA resulting in data
overwriting. To keep the consistency with other parts of the DC code,
this commit changes dc_commit_streams to copy the current DC state, and
as a result, it also changes the function signature to expect streams
instead of a context.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Co-developed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Change commit sequence will impact all ASICs. It is prudent to run this
update in small steps to keep issues under control and avoid any
potential regression. With this idea in mind, this commit is preparation
work for the complete transition to the new commit sequence. To maintain
this change manageable across multiple ASICs, this commit adds a new
function named dc_commit_streams which is a copy of the dc_commit_state
with some minor changes. Finally, inside the dc_commit_state, we check
if we are using DCN32x or above and enable the new sequence only for
those devices.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Co-developed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC version 3.2.207 brings along the following:
- PMFW z-state interface update
- Cursor update refactor
- Fixes to DSC validation, DCFCLK during Freesync, etc.
- Code cleanup
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Dpia hpd interrupt processing is disabled when entering S4/S0i3 and
would be reenabled after detection completes during resuming. Because,
keeping hpd interrupts enabled during detection leads to multiple
detections for the same hpd transition. There is a S4 case where dpia
hpd interrupt is missed when driver is in transitioning from hpd
interrupt processing disable to enable and the display does not light
up.
[How]
- Added dmub inbox command DMUB_CMD__DPIA_HPD_INT_ENABLE to explicitly
control dmub to issue dpia hpd interrupt or not. If dpia hpd interrupt
is disabled, dmub will keep the hpd pending and post it once driver
reenables dpia hpd interrupt or when querying with
DMUB_CMD__QUERY_HPD_STATE.
- Added dmub boot option dpia_hpd_int_enable_supported to notify dmub
about whether DMUB_CMD__DPIA_HPD_INT_ENABLE command would be used.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Mustapha Ghaddar <Mustapha.Ghaddar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
Add a helper to map ODM/MPC/Multi-Plane resources from DC
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Jun Lei <jun.lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
We split out ILR config from "global" to "per-panel" config settings.
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- LTTPR mode can be be dynamically changed
- fixes divide by zero error
- features able to use same interface to update cursor info
- fixes for llvm compilation issues
- Fixes DIO FIFO underflow and other FIFO errors
- Partially valid EDIDs handled properly
- Phatom pipes are skipped when checking pending flip
- Fixed audio on audio on display after unplugging
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
Several transitions were fixed that will allow Dynamic ODM and MPO
transitions to be supported on DCN32.
1) Due to resource limitations, in certain scenarios that require an MPO
plane to be split, the features cannot be combined with the current
policy. This is due to unsafe transitions being required (OPP instance
per MPCC being switched on active pipe is not supported by DCN), to
support the split plane with ODM active as it moves across the viewport.
Dynamic ODM will now be disabled when MPO is required.
2) When exiting MPO and re-entering ODM, DC assigns an inactive pipe for
the next ODM pipe, which under previous power gating policy would result
in programming a gated DSC HW block. New policy dynamically
gates/un-gates DSC blocks when Dynamic ODM is active to support
transitions on DCN32 only.
3) Entry and exit from 3 plane MPO and Dynamic ODM requires a minimal
transition so that all pipes which require their MPCC OPP instance to
be changed have a full frame to be disabled before reprogramming. To
solve this, the Dynamic ODM policy now utilizes minimal state
transitions when entering or exiting 3 plane scenarios.
4) Various fixes to DCN32 pipe merge/split algorithm to support Dynamic
ODM and MPO transitions.
In summary, this commit fixes various transitions to support ODM->MPO
and MPO->ODM.
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
Update MALL SS NumWays calculation according
to programming guide.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Don't use MALL buffering of any kind when the
surface is TMZ
- Workaround for a HW bug
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
adding debug keys used for compliance test.
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Fix urgent latency override for DCN32/DCN321
- Correct hostvm flag in DCN31
- Added new Asic Id for DCN301
- Adjust to 2 phys in DCN301
- Update dummy P-state search to use DCN32 DML
- Increase dcn315 pstate change latency
- Disable OTG WA for the plane_state NULL case on DCN314
- Update dccg based on HW delta
- Correct num_dsc for DCN314
- Fix DP DSC compliance failure with DCN314
- Refactor edp power sequencer codes
- update gamut remap if plane has changed
- Skip audio setup when audio stream is enabled
- Display distortion after hotplug LG Ultrafine 5K tiled display
- Fix DP MST timeslot issue when fallback happened
- Uncomment SubVP pipe split assignment in driver
- Enable committing subvp config
- Do second pass through DML for DET calculation
- Don't allocate DET for phantom pipes
- Modify DML to adjust Vstartup Position
- Ignore k1/k2 values for virtual signal to avoid assert
- Fix failures of disabling primary planes
- Do not compare integers of different widths
- Fix empty slot problem of EDID management
- Revise Sink device string ID width in dmub psr
- Log vertical interrupt 1 for debug
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Port DCN30 420 logic to DCN32
- Remove some unused definitions from DCN32/321
- Remove dp dig pixle rate div policy from dcn314
- Fix dcn315 reading of memory channel count and width
- Fix SubVP and ODM relevant issues
- Fix pipe split, MPO and ODM relevant issues
- Support proper mst payload removal when link is not in mst mode in dc
- Assume an LTTPR is always present on fixed_vs links
- Rework recent update PHY state commit
- Add debug option and logs
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why and How]
- Add a debug option for allocating extra way for cursor
- Remove usage of cache_cursor_addr since it's not gaurenteed
to be populated
- Include cursor size in MALL calculation if it exceeds the
DCN cursor buffer size (and don't need extra way for cursor)
Reviewed-by: Aurabindo Pillai <Aurabindo.Pillai@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
*Fixed register definitions for DCN32/321
*Adding log for spread_spectrum_info
*Reverted DSC programming sequence change
*Correct I2C register offset
*Updated DCN30 header files, viewport position for phantom pipes
*Enable dlg and vba compilation for dcn314
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
Regkey option for forcing num ways for subvp for debug purposes
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
Leverage SW cursor fall back for SubVP when the cursor is too big. We
want to take advantage of being able to fallback to SW cursor when
possible because it's not worth it to disable MCLK switching because the
cursor is slightly too big.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aurabindo Pillai <Aurabindo.Pillai@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why && How]
We would like to have visual confirm color support for SubVP.
1. Set visual confirm color to red: SubVP is enable on this
display;
2. Set visual confirm color to green: SubVP is enable on
other display and DRR is on this display;
3. Set visual confirm color to blue: SubVP is enable on
other display and DRR is off on this display;
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Refactor edp dsc codes.
We split out edp dsc config from "global" to "per-panel" config settings.
Reviewed-by: Mike Hsieh <mike.hsieh@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
We want to get the visual confirm color of the bottom-most pipe
for test automation.
[How]
Save the visual confirm color to plane_state before program to MPC;
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
enable_sw_cntl_psr flag is not needed.
For PSR1 and PSR2, we should be passing
dirty rectangle and cursor updates to FW
regardless of enable_sw_cntl_psr flag.
[How]
Remove enable_sw_cntl_psr flag from driver.
Send cursor info and dirty rectagle status to
dmub only in the case of dcn31 and above.
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Robin Chen <robin.chen@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Useful for external teams debugging LTTPR issues
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
RV2 do not change pipe split policy in the
minimal pipe split transition state.
This will unblock mode support on some
parts that limit to DPM0 for power reason.
[How]
Do not change pipe split policy in the
minimal pipe split transition state to
allow 4k multi display configs to be
supported at DPM0.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Derek Lai <Derek.Lai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This verion brings along following fixes:
-Add scaling factor for SubVP
-Modify stop_dbg_mode return value
-Add gfx_off members and document
-Add GFXOFF function for vangogh
-Add GFXOFF stats to debug
-Fix codestyle problems
-Fix overflow on MIN_I64
-Fix Unneeded semicolon
-Fix comment typo
-Remove useless condition in amdgpu_job_stop_all_jobs_on_sched()
-Add decoder_iv_ts helper for ih_v6
-Add chip version to DCN32
-Avoid doing vm_init multiple time
-Modify size calculation in MALL
-Fix DSC for phantom pipes
-Update clock table policy for DCN314
-Modify header inclusion pattern
-Fix plug/unplug external monitor will playback MPO video
-Add debug parameter to retain default clock table
-Increase tlb flush timeout for sriov
-Fix compare intergers of different widths
-Add reserved dc_log_type
-Fix pixel clock programming
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Currently, we are using soc._clock_tmp[] to temporarily store and modify
data from soc.clock_limits[] before copying it back into
soc.clock_limits[] (because modifying data directly in
soc.clock_limits[] causes unintended behavior). However, this approach
has a number of downsides, such as:
1. struct _vcs_dpi_soc_bounding_box_st's creation/destruction
aren't well defined (which could mean more unintended
behavior).
2. Throwing "temp" varibles in structs everywhere doesn't make
for a particularly readable codebase.
For these reasons, we should get rid of soc._clock_tmp[] by defining a
struct scratch within struct dc that, contains within it all of the
temporary variables (including _clock_tmp[]) such that it is obvious how
they are intended to be used.
Co-authored-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add details about color correction capabilities and explain a bit about
differences between DC hw generations and also how they are mapped
between DRM and DC interface. Two schemas for DCN 2.0 and 3.0 (converted
to svg from the original png) is included to illustrate it. They were
obtained from a discussion[1] in the amd-gfx mailing list.
[1] https://lore.kernel.org/amd-gfx/20220422142811.dm6vtk6v64jcwydk@mail.igalia.com/
v1:
- remove redundant comments (Harry)
- fix typos (Harry)
v2:
- reword introduction of color section
- add co-dev tag for Harry - who provided most of the info
- fix typos (Tales)
- describe missing struct parameters (Tales and Siqueira)
Co-developed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Melissa Wen <mwen@igalia.com>
Reviewed-by: Tales Aparecida <tales.aparecida@gmail.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
In the DCN code, we can find some references to three different pipe
split policies but no clear description. This commit adds some
kernel-doc that explains more about these options and a little bit of
their impact.
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Need a way to retain default clock table to aid
the investigation into why 8k@30 display not
lighting up on dcn314
[How]
Use flag to prevent execution of bw_params helper
function and function for updating bw_bounding_box
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Daniel Miess <Daniel.Miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
-Fix edp panel missing event
-Set ARGB16161616 pixel format to 26
-Fix dcn32 interger issue
-Clear optc underflow bit after ODM clock off
-Fix issue with stereo3D
-Fix DML2 lightup issue
-Correct DTBCLK for dcn314
-Revert for a regression
-Fix clocks and bugs in DML2
-Enable SubVP by defalut on DCN32 & DCN321
-Corret boundary condition for engin ID on DCN303
-Fix FRL encoder override registry key
-Fix VPG for dcn314 HPO
-Fix Linux compile-time warning
-Add new prefetch modes in DML for DCN32
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Move fpu file to dml folder
- Fix CAB allocation for multiple displays
- Add a variable to update FCLK
- Fix TMDS 4K@60Hz YCbCr420 corruption issue
- Fix MPC tree infinite loop in some case
- Fix HDMI VSIF V3 blank screen issue
- Add some documentation to the code
- Allow alternate prefetch modes in DML for DCN32
- Fix VPG instancing for dcn314 HPO
- Check correct bounds for stream encoder instances for DCN303
- Enable SubVP by default on DCN32 & DCN321
- Fix DTBCLK not correct for dcn314
- Fix Compile-time warning
- Fix the stereo mode hang issue
- Fix display light up issue
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
SUBVP_START_LINE must be aligned to 2 swaths, so add
16 lines of margin so the start line can be adjusted by
up to 16 lines for alignment purposes in FW.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Driver is restricting voltage levels if system cannot switch
in vblank.
[How]
Change allow_for_pstate_or_stutter_in_vblank_final from
dm_prefetch_support_uclk_fclk_and_stutter to
dm_prefetch_support_uclk_fclk_and_stutter_if_possible.
Add support for a new registry property,
DalDMLDisallowAlternatePrefetchModes, for easier debugging.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
Add a variable to update FCLK latency
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Copy crc_skip_count when duplicating CRTC state
- Add debug option for idle optimizations on cursor updates
- Disable MPC split for DCN32/321
- Add missing ODM 2:1 policy logic
- Update DCN32 and DCN321 SR latencies
- Add reinstate dram in the FPO logic
- Add dc_ctx to link_enc_create() parameters
- Cache cursor when cursor exceeds 64x64
- Add support for manual DMUB FAMS trigger
- Fix dpstreamclk programming
- Add missing AUDIO_DTO_SEL reg field
- Add OTG/ODM functions
- Use correct clock source constructor for DCN314
- Use correct DTO_SRC_SEL for 128b/132b encoding
- Add pixel rate div calcs and programming
- Remove FPU flags from DCN30 Makefile
- Create patch bounding box function for isolate FPU
- Move mclk calculation function to DML
- Remove FPU operations from dcn201 resources
- Fallback to SW cursor if SubVP + cursor too big
- Drop unnecessary FPU flags on dcn302 files
- Reboot while unplug hdcp enabled dp from mst hub
- Reset pipe count when iterating for DET override
- Calculate MALL cache lines based on Mblks required
- Fix two MPO videos in single display ODM combine mode
- Guard against zero memory channels
- Updates SubVP + SubVP DRR cases updates
- Fix OPTC function pointers for DCN314
- Add enable/disable FIFO callbacks to stream setup
- Avoid MPC infinite loop
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Anthony Koo <anthony.koo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Isolate FPU operation for DCN32/321 under the DML folder
- Create a specific file for CRTC and plane based on amdgpu_dm
- Fix DSC issues
- Update DML logic
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Remove an unused variable "remove_disconnect_edp" which was a workaround
bit.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Fixes for MST, MPO, PSRSU, DP 2.0, Freesync and others
- Add register offsets of NBI and DCN.
- Improvement of ALPM
- Removing assert statement for Linux DM
- Re-implementing ARGB16161616 pixel format
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
Add a field to store the NBIO IP offset for use with runtime offset
calculation
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
Add a field to store the DCN IP offset for use with runtime offset
calculation
This offset is indexed using reg*_BASE_IDX for the corresponding
group of registers. For example, address of DIG_BE_CNTL instance 0 is
calculated like: dcn_reg_offsets[regDIG0_DIG_BE_CNTL_BASE_IDX] +
regDIG0_DIG_BE_CNTL.
{dcn,nbio}_reg_offsets are used only for the ASICs for which runtime
initializaion of offsets are enabled through the modified SR* macros
that contain an additional REG_STRUCT element in the macro definition.
DCN3.5+ will fail dc_create() if {dcn,nbio}_reg_offsets are null. They
are applicable starting with DCN32/321 and are not used for ASICs
upstreamed before them. ASICs before DCN32/321 will not contain any
computation that involves {dcn,nbio}_reg_offsets. For them, the
address/offset computation is done during compile time.
This is evident from the BASE_INNER definition for compile time vs run
time initialization:
Compile time init: #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
Run time init: #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
BASE_INNER macro is local to each dcnxx_resource.c and hence different
ASICs can have either runtime or compile time initialization of offsets.
The computation of offset is done for registers all at once during
driver load and hence it does not introduce any performance overhead
during normal operation.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
Exit SubVP if MPO is in use since SubVP + MPO together is not supported.
- Don't add SubVP at validation time if we see MPO is in use
Issues fixed in the SubVP / MPO transition:
1. Enable phantom pipes in post unlock function to prevent underflow
when an active pipe is being transitioned to be a phantom pipe (VTG
updates take place right away). Also must wait for VUPDATE of the main
pipe to complete first
2. Don't wait for MPCC idle when transitioning a phantom pipe to an
actual pipe. MPCC_STATUS is never asserted due to OTG being off for
phantom pipes
3. When transitioning an active pipe to phantom, program DET right away
(same as disabling the pipe) or the DET update will only take when
the phantom pipe is enabled which can cause DET allocation errors.
4. For K1/K2 programming of phantom pipes, use same settings as the
main pipe. Also don't program K1 / K2 = 0xF ever since the field is only
1 / 2 bits wide.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Program ACP-related registers
- Fixes for DMUB, DPIA, PSR, and others
- Improvements in the pipe split
- Add SubVP code
- Add basic setup for FAMS support
- Improve BB capabilities
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hdmi_frl_pcon_support has been the source of confusion. So, rename it to
dp_hdmi21_pcon_support.
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Some panels may require more MST delay on discovery
[How]
Add panel patch and debug mst delay flag
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Some TBT3 docks have DPOAs which report USB4 capability and are expected
to support USB4 DPOA features such as FEC/DSC.
[How]
By default, do not override FEC/DSC capabilities reported by TBT3 docks.
Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DC debug option to configure dpia hpd processing delay is not required.
[How]
Remove dc debug option for dpia hpd delay and also added log for
querying dpia hpd state.
Reviewed-by: Mustapha Ghaddar <Mustapha.Ghaddar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
We want to enable Firmware Assisted Memory (FAMS) Switching, but first,
we need to add the required code infrastructure in DC before allowing it
in amdgpu_dm.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Newer DCN should use optc3
[How]
Declare optc3 vmin/vmax function in header.
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Most of the time, a single display uses the ODM combine. When using
multi-display, we use ODM combine only if it is necessary. These cases
are not flexible enough for us, and we can improve them to take
advantage of our hardware. We want to have more control over the ODM
policy.
[How]
This commit add a new debug flag named
enable_single_display_2to1_odm_policy to control the ODM policy and
another flag named enable_dp_dig_pixel_rate_div_policy to fine control
the ODM combine. This is possible by adding a new "pipe.dest" parameter
that can be set to ODM 2:1 combined if we use a single display. For
dynamic ODM combine, when using DP-DIG, DCN applies K2=2 settings for
ODM combine. Note that this feature affects the following registers:
- timing.pix_clk_100khz -> DP_VID_M, DP_VID_N
- requested_pix_clk_100hz -> DP_DTOn_PHASE
- OTGn_PIXEL_RATE_DIVK2
- DP_PIXEL_PER_CYCLE_PROCESSING_MODE
- DIG_FIFO_OUTPUT_PIXEL_MODE
- DP_VID_N_MUL
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit enables the SubVP feature. To achieve that, we need to:
- Don't force p-state disallow on SubVP (can't block dummy p-state)
- Send calculated watermark to DMCUB for SubVP
- Adjust CAB mode message to PMFW
- Add a proper locking sequence for SubVP
- Various fixes to SubVP static analysis and determining SubVP config
- Currently SubVP not supported with pipe split so merge all pipes
before setting up SubVp
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Remove unnecessary code;
- Small fixes (compilation warnings, typos, etc);
- Improvements in the DPMS code;
- Fix eDP issues
- Improvements in the MST code
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
Old vendor specific w/a are no longer needed and unused. Clean up
codebase by removing them.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Several issues were discovered that caused link
training to fail when an LTTPR device is
connected downstream for the fixed VS sequence.
[How]
The following were added:
- workaround to configure AUX timeout
for fixed VS sequence
- additional delay before disabling
fixed VS intercept
- detection of fixed VS deadlock state and
performing DPCD sequence to recover
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: George Shen <George.Shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Only on VG, if external display is disconnected during S3 suspend, the
internal panel doesn't light up on resume because we set the power state
using an unsupported DPCD register SET_POWER. To check the register is
supported, we need to check SET_POWER_CAPABLE first which is
eDP-specific DPCD register field.
[how]
Check the SET_POWER_CAPABLE register field and decide the control of the
eDP power state based on the read register value.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Agustin Gutierrez <Agustin.Gutierrez@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
All displays need to be blanked during the uclk OC interface so that we can
guarantee pstate switching support. If the display config doesn't support
pstate switching, only using core_link_disable_stream will not enable it
as the front-end is untouched. We need to go through the full plane removal
sequence to properly program the pipe to allow pstate switching.
[How]
- guard clk_mgr functions with non-NULL checks
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- DP fixes
- Exiting idle optimizations on mouse updates
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Have option to exit idle opt on cursor updates
for debug and optimizations purposes
Reviewed-by: Samson Tam <Samson.Tam@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- DPP DTO fix
- Transient encoder fix
- Restrict the reading of LTTPR capabilities in LTTPR mode
- Increase maximum stages for BB
- Distinguish HDMI DTO from DP DTO
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Some parts are consuming dangerously close to maximum number of states
supported when updating the BB (i.e. 8).
[how]
Change maximum stages from 9 to 20.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Jun Lei <jun.lei@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- Optimized blank calculations
- More robust DP MST hotplug support
- eDP bug fix relating to ODM
- Revert a patch that caused a regression with DP
- min comp buffer size fix
- Make DP easier to debug
- Calculate the maximum OLED brightness correctly
- 3 plane MPO.
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
For panels with pixel clock > 1200MHz that require ODM
in pre-OS, when driver is disabled in OS, odm is enabled.
Upon driver enablement, corruption is seen if
odm was originally enabled. DP_PIXEL_COMBINE and
pixelclk must be programmed prior to programming the
optc-odm registers. However, eDP displays aren't blanked
prior to initializing odm in this case.
[How]
Upon driver enablement, check whether odm is enabled,
if so, blank eDP prior to programming optc-odm
registers.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY & HOW]
Implements DTB ref clock switching with reg key default to OFF.
Refactors dccg DTBCLK logic to not store redundant state information
dccg. Also removes duplicated functions that should be inherited from
other dcn versions.
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
This patch adds necessary changes needed in DC files outside DCN32/321
specific tree
v2: squash in updates (Alex)
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
why:
lut pipeline will be hooked up differently in some asics
need to add new interfaces
how:
add them
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Martin <martin.leung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following fixes:
* Changes to DP LT fallback behavior to more closely match the DP standard
* Added new interfaces for lut pipeline
* Restore ref_dtblck value when clk struct is cleared in init_clocks
* Fixes DMUB outbox trace in S4
* Fixes lingering DIO FIFO errors when DIO no longer enabled
* Reads Golden Settings Table from VBIOS
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
why and how:
Revert this change. It was causing a black screen with certain blocks
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Leung, Martin <Martin.Leung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
According to the KMS man page, there is a
"Coverage" alpha blend mode that assumes the
pixel color values have NOT been pre-multiplied
and will be done when the actual blending to
the background color values happens.
Previously, this mode hasn't been enabled
in our driver and it was assumed that all
normal overlay planes are pre-multiplied
by default.
When a 3rd party app is used to input a image
in a specific format, e.g. PNG, as a source
of a overlay plane to blend with the background
primary plane, the pixel color values are not
pre-multiplied. So by adding "Coverage" blend
mode, our driver will support those cases.
Issue fixed: Overlay plane alpha channel blending is incorrect
Issue tracker: https://gitlab.freedesktop.org/drm/amd/-/issues/1769
Reference:
https://dri.freedesktop.org/docs/drm/gpu/drm-kms.html#plane-composition-properties
Adding Coverage support also enables IGT
kms_plane_alpha_blend Coverage subtests:
1. coverage-7efc
2. coverage-vs-premult-vs-constant
Changes
1. Add DRM_MODE_BLEND_COVERAGE blend mode capability
2. Add "pre_multiplied_alpha" flag for Coverage case
3. Read the correct flag and set the DCN MPCC
pre_multiplied register bit (only on overlay plane)
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1769
Signed-off-by: Sung Joon Kim <Sungjoon.Kim@amd.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along the following:
- Improvements in link training fallback
- Adding individual edp hotplug support
- Fixes in DPIA HPD status, display clock change hang, etc.
- FPU isolation work for DCN30
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Second eDP can send display off notification through HPD
but DC isn't hooked up to handle. Some primary eDP panels
will toggle on/off incorrectly if it's enabled generically.
[How]
Extend the debug option to allow individually enabling hotplug
either the first eDP or the second eDP in a dual eDP system.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Derek Lai <Derek.Lai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Refactor LTTPR code
- Fix PSR after hibernate
- Fix DC build errors
- Fix IRQ unregister error when unloading amdgpu
- Improve DP link training
- Fix stutter
- Remove redundant CONFIG_DRM_AMD_DC_DCN guards
- Fix 2nd connected USB-C display not lighting up
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.
This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
in dc and dc/core directories.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
Move definition of dc_flip_addrs struct from dc.h to dc_hw_types.h to
prevent build errors
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Have optc3 function accessible to newer DCN
- Add CM boot option for USB4 tunneling
- Fix system hang issue when game resolution is changed
- Remove outdated register for dcn3+
- Add new DSC interface to disconnect from pipe
- Clean up pixel format types in enum surface_pixel_format
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Keep tracking of DSC packed PPS for future use
- Maintain current link settings in link loss interrupt
- Remove DDC write and read size check
- Read PSR-SU cap DPCD for specific panel
- Don't pass HostVM by default on DCN3.1
- Reset cached PSR parameters after hibernate
- Add audio readback registers
- Update dcn315 clk table read
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Integer no longer needed.
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Roll back previous change to stop passing this value by default, instead
add a debug flag to override to previous behaviour (or force HostVM calcs)
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following improvements:
- Fix HDCP QUERY Error for eDP and Tiled
- Insert smu busy status before sending another request
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Title: DC Patches Apri 6, 2022
This DC patchset brings improvements in multiple areas. In summary, we highlight:
*Disabling Z10 on DCN31
*Fix issue breaking 32bit Linux build
*Fix inconsistent timestamp type
*Add DCN30 support FEC init
*Fix crash on setting VRR with no display connected
*Disable FEC if DSC not supported for EDP
*Add odm seamless boot support
*Select correct DTO source
*Power down hardware if timer not trigger
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Implement changes to transition from Pre-OS odm to
Post-OS odm support. Seamless boot case is also
considered.
[HOW]
Revised validation logic when marking for seamless
boot. Init resources accordingly when Pre-OS has
odm enabled. Reset odm and det size when transitioning
Pre-OS odm to Post-OS non-odm to avoid corruption.
Apply logic to set odm accordingly upon commit.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Duncan Ma <Duncan.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
dcn316's dtbclk is from non_ss clock source.
no compensation required here.
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
- [FW Promotion] Release 0.0.111.0
- Check for invalid input params when building scaling params
- Move link_trace for edp to dp_trace
- Fix missing-prototypes warning
- Enable 3 plane for DCN 3.0 and 3.02
- Extract set stream attribute into link_hwss
- Revert Power down hardware if timer not trigger
- Add support for handling 128b/132b link training test request
- Add configuration options for AUX wake work around
- Remove underflow IRQ type
- Add flip interval workaround for low FPS in some game
- Remove assert for odm transition case
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Work around to try to wake unresponsive DP sinks may need to be adjusted
for certain sinks.
[How]
Add options to disable work around or adjust time spent trying to wake
unresponsive DPRX.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
- [FW Promotion] Release 0.0.110.0
- Revert FEC check in validation
- Update LTTPR UHBR link rate support struct
- Add support for USBC connector
- Add work around for AUX failure on wake
- Clear optc false state when disable otg
- Enable power gating before init_pipes
- Remove redundant dsc power gating from init_hw
- Power down hardware if timer not trigger
- Correct Slice reset calculation
- Enable 3-plane MPO for DCN31
- Set fec register init value
- Remove SW w/a for HDCP 1.4 1A-07 failure based on ECO fix
- Create underflow interrupt IRQ type
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- HDCP SEND AKI INIT error
- fix audio format not updated after edid updated
- Reduce stack size
- FEC check in timing validation
- Add fSMC_MSG_SetDtbClk support
- Update VTEM Infopacket definition
- [FW Promotion] Release 0.0.109.0
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
When we enter FREESYNC_STATE_VIDEO, we want to use the extra vblank
portion to enter zstate if possible.
[how]
When we enter freesync, a full update is triggered and the new vtotal
with extra lines is passed to dml in a stream update. The time gained
from extra vblank lines is calculated in microseconds. We allow zstate
entry if the time gained is greater than 5 ms, which is the current
policy. Furthermore, an optimized value for min_dst_y_next_start is
calculated and written to its register. When exiting freesync, another
full update is triggered and default values are restored.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Added I2C escape to support query exist
- Functionality to get pipe from stream context
- debugfs entry fixes
- Block zstate when more than one plane enabled
- Update to engine ddc
- Reading lante status during LT fixes
- Null point filters
- [FW Promotion] Release 0.0.108.0
Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: 3.2.176
This version brings along following fixes:
- move FPU operations from dcn21 to dml/dcn20 folder
- move FPU-related code from dcn20 to dml folder
- Fix compile error from TO_CLK_MGR_INTERNAL
- Fix double free during GPU reset on DC streams
- Add NULL check
- [FW Promotion] Release 0.0.107.0
- enable dcn315/316 s0i2 support
- handle DP2.0 RX with UHBR20 but not UHBR13.5 support
- disable HPD SW timer for passive dongle type 1 only
- add gamut coefficient set A and B
- merge two duplicated clock_source_create
- Add link dp trace support
- move FPU associated DCN303 code to DML folder
- Release AUX engine after failed acquire
- Add minimal pipe split transition state
- Clean up fixed VS PHY test w/a function
- fix the clock source contruct for dcn315
- cleaning up smu_if to add future flexibility
- fix deep color ratio
- add debug option to bypass ssinfo from bios for dcn315
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Need to provide this workaround
only for type 1 passive dongle
[how]
Detect if dongle is type 1 or 2.
And use it to determine if w/a is needed.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: 3.2.175
This version brings along following fixes:
- Remove invalid RDPCS Programming in DAL
- Make functional resource functions non-static
- Reset VIC if HDMI_VIC is present
- Add frame alternate 3D & restrict HW packed on dongles
- Reg to turn on/off PSR Power seq in FSM
- Modify plane removal sequence to avoid hangs
- Pass HostVM enable flag into DCN3.1 DML
- DC Validation failures
- Program OPP before ODM
- Refactor fixed VS w/a for PHY tests
- Pass deep sleep disabled allow info to dmub fw
- Refine the EDID override
- [FW Promotion] Release 0.0.106.0
- Add verify_link_cap back for hdmi
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
The deep sleep mode need to be disabled in some PSR scenario.
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Robin Chen <robin.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
PSR Power on/off is done in PSR. Add a dc_debug option
and dmub setting to use PHY implementation of this instead.
[How]
Add a dc_debug option and dmub setting to use
PHY FSM Power up/down for PSR.
Co-authored-by: Shah Dharati <dharati.shah@amd.com>
Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Shah Dharati <dharati.shah@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- add debug option to bypass ssinfo from bios.
- Refactor fixed VS logic for non-transparent mode
- add cable ID support for usb c connector
- clear remote dc_sink when stop mst
- Ignore Transitional Invalid Link Rate Error Message
- Fix wrong resolution with DP/VGA adapter
- Refactor PSR DPCD caps detection
- Set compbuf size to min at prep prevent overbook crb
- lock/un-lock cursor if odm pipe split used
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
add debug option to bypass ssinfo from bios.
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[how]
Call to DMUB to retrieve usb c cable ID data from PD firmware.
If cable id is retrieved from DMUB, skip reading cable ID from RX.
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas
Aric Cyr
Duncan Ma
Aurabindo Pillai
Sung Joon Kim
Mario Limonciello
Mounika Adhuri
Qingqing Zhuo
Sung Joon Kim
Wenjing Liu
Ovidiu Bunea
Max Tseng
Gabe Teeger
Dmytro Laktyushkin
Ethan Bitnun
Martin Leung
Mustapha Ghaddar
Ian Chen
Michael Strauss
Bhawanpreet Lakha
Alvin Lee
Reza Amini
George Shen
Nicholas Susanto
Randy Dunlap
Gianna Binder
Ilya Bakoulin
Austin Zheng
Cruise Hung
Leo (Hanghong) Ma
Leo Chen
Arnd Bergmann
Michael Mityushkin
Artem Grishin
Rodrigo Siqueira
David Tadokoro
Harry Wentland
Charlene Liu
Dillon Varone
Jun Lei
Meenakshikumar Somasundaram
Derek Lai
Hamza Mahfooz
Melissa Wen
Daniel Miess
David Galiffi
Anthony Koo
Jimmy Kizito
Samson Tam
Joshua Aberback
Alex Hung
Josip Pavic
Robin Chen
Shah Dharati