2 Commits

Author	SHA1	Message	Date
Chao Xie	38f2e37724	ARM: cache: add extra feature enable for tauros2 ... The extra feature may be used by SOCs are prefetch, burst8, write buffer coalesce Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>	2012-08-16 16:16:27 +08:00
Lennert Buytenhek	573a652fb0	ARM: Add Tauros2 L2 cache controller support ... Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>	2009-11-27 15:43:21 -05:00