mirror of https://github.com/torvalds/linux.git
12 Commits
| Author | SHA1 | Message | Date |
|---|---|---|---|
Martin Blumenstingl
|
087a1d8b4e |
ARM: dts: meson8b: ec100: add the VDDEE regulator
The VDDEE regulator is basically a copy of the VCCK regulator. VDDEE supplies for example the Mali GPU and is controlled by PWM_D instead of PWM_C. Add the VDDEE PWM regulator and make it the supply of the Mali GPU. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> |
|
|
Martin Blumenstingl
|
a2c6e82e53 |
ARM: dts: meson: switch to the generic Ethernet PHY reset bindings
The snps,reset-gpio bindings are deprecated in favour of the generic "Ethernet PHY reset" bindings. Replace snps,reset-gpio from the ðmac node with reset-gpios in the ethernet-phy node. The old snps,reset-active-low property is now encoded directly as GPIO flag inside the reset-gpios property. snps,reset-delays-us is converted to reset-assert-us and reset-deassert-us. reset-assert-us is the second cell from snps,reset-delays-us while reset-deassert-us was the third cell. Instead of blindly copying the old values (which seems strange since they gave the PHY one second to come out of reset) over this also updates the delays based on the datasheets: - RTL8211F PHY on the Odroid-C1 and MXIII-Plus needs a 10ms assert delay (the datasheet mentions: "For a complete PHY reset, this pin must be asserted low for at least 10ms") and a 30ms deassert delay (the datasheet mentions: "Wait for a further 30ms (for internal circuits settling time) before accessing the PHY register"). The old settings used 10ms for assert and 1000ms for deassert. - IP101GR PHY on the EC-100 and MXQ needs a 10ms assert delay (the datasheet mentions: "Trst | Reset period | 10ms") and a 10ms deassert delay as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock output ready after reset released | 10ms")). The old settings used 10ms for assert and 1000ms for deassert. No functional changes intended. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> |
|
|
Martin Blumenstingl
|
6ffdc4738c |
ARM: dts: meson8b: ec100: enable the RTC
The RTC is always enabled on this board since the battery is already connected in the factory. According to the schematics the VCC_RTC regulator (which is either powered by the internal 3.3V or a battery) is connected to the 0.9V RTC_VDD input of the SoCs. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> |
|
Linus Torvalds
|
6ad63dec9c |
ARM: SoC device tree updates for 5.1
This is a smaller update than the past few times, but with just over
500 non-merge changesets still dwarfes the rest of the SoC tree.
Three new SoC platforms get added, each one a follow-up to an existing
product, and added here in combination with a reference platform:
- Renesas RZ/A2M (R7S9210) 32-bit Cortex-A9 Real-time imaging processor
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza2m.html
- Renesas RZ/G2E (r8a774c0) 64-bit Cortex-A53 SoC "for
Rich Graphics Applications".
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg2e.html
- NXP i.MX8QuadXPlus 64-bit Cortex-A35 SoC
https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X
These are actual commercial products we now support with an in-kernel
device tree source file:
- Bosch Guardian is a product made by Bosch Power
Tools GmbH, based on the Texas Instruments AM335x chip
- Winterland IceBoard is a Texas Instruments AM3874 based
machine used in telescopes at the south pole and elsewhere, see commit
|
|
Arnd Bergmann
|
f815bb4e97 |
ARM: dts: Amlogic updates for v5.1
- more features for Endless EC100 board - chip temperature sensor support - fix ethernet pins - add Mali-450 GPU -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAlxh4LQACgkQWTcYmtP7 xmWu3w//bOc1aqMh325KmhP+WXUJEp0Z+7/r8TcqYYW2UMdjqGKvYNREaL+cDKu3 6DOaWvTKrRHOJr1L4uSdg1NBEhH6Nzmb7r9bRLkj2xT5vT66pZIiMa4OETfvdvP2 TQ86MPUY69M6IJ2JzeYA34stItYanExDhosbaHmPSJqwvDdh0V932eBg4OY/IpEn j4Hygf9HYSA5cSx7J2Ah1gUXzI66FcPlRBWrl+jeTS7qqU9GxYo8/8Hrgn6hyCTQ dpQHvgsCdeHvsf8fRpulxH/aUo5u2nuX1/R8UrOWUmCPd2r3RBu0U27Ja7FJiAeb s6OwLveAVeMS7Urrh3ylaFstbjg3CMtGvh1hnbWozF08yNzd6ihD5vsUED7vpxNr hT8m8oC8hujP1CiIxFqbkPZsz/hWoagPOG2AtRNMehs+gVxOfD+CTkw3Y+x3+NrA DwU9YzrKqFn4StSHJ6ccBE857gSH5QgOq0rLYiH1AlktHvXKh/hL/H82pFDJHZcW OFZ2nAI9VCPDlx8tCbuH16BIqD03piT5ew0wWozG5uc/JP26stmMXHQlQVDxRju4 NsJiqGzAtgIK+jf2COVZJeYtOO9IYjPwrC0wJe2vWW7MTUBv0LSQDuBV2pTT/N87 pSqeusg80DuPC3WZLGU3whitwO6yg3NiWeGB6cweu3gWeQsMSig= =PNC5 -----END PGP SIGNATURE----- Merge tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt ARM: dts: Amlogic updates for v5.1 - more features for Endless EC100 board - chip temperature sensor support - fix ethernet pins - add Mali-450 GPU * tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM: dts: meson8b: ec100: add the GPIO line names ARM: dts: meson8b: ec100: improve the description of the regulators ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature ARM: dts: meson8b: add the temperature calibration data for the SAR ADC ARM: dts: meson8: add the temperature calibration data for the SAR ADC ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible ARM: dts: meson: switch the clock controller to the HHI register area ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins ARM: dts: meson8b: add the Mali-450 MP2 GPU ARM: dts: meson8: add the Mali-450 MP6 GPU dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible ARM: dts: meson8b: add the APB bus ARM: dts: meson8: add the APB bus ARM: dts: meson6: add the APB2 bus Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
|
|
Martin Blumenstingl
|
99f0619b0d |
ARM: dts: meson8b: ec100: add the GPIO line names
This adds the GPIO line names from the schematics to get them displayed in the debugfs output of each GPIO controller. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> |
|
|
Martin Blumenstingl
|
3e7db1c1b7 |
ARM: dts: meson8b: ec100: improve the description of the regulators
USB_VBUS is a controlled by a Silergy SY6288CCAC-GP 2A Power Distribution Switch. The name of it's enable GPIO signal is USB_PWR_EN. VCC5V is supplied by the main power input called PWR_5V_STB. The name of it's enable GPIO signal is 3V3_5V_EN. VCC3V3, VCC_DDR3_1V5 and VCCK (the CPU power supply) each use a separate Silergy SY8089AAC-GP 2A step down regulator. They are all supplied by the board's main 5V. VCC3V3 and VCC_DDR3_1V5 are fixed regulators while the voltage of VCCK can be changed by changing it's feedback voltage via PWM_C. VCC1V8 is an ABLIC S-1339D18-M5001-GP fixed voltage regulator which is supplied by VCC3V3. VCC_RTC is a Global Mixed-mode Technology Inc. G918T12U-GP LDO which. It is supplied by either VCC3V3 (when the board is powered) or the RTC coin cell battery. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> |
|
|
Martin Blumenstingl
|
b7d10841e5 |
ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt
The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad on the SoC. Enable the interrupt function of the PHY's INTR32 pin to switch it from it's default "receive error" mode to "interrupt pin" mode. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> |
|
|
Martin Blumenstingl
|
1a4f28ab25 |
ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature
SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> |
|
Rob Herring
|
abe60a3a7a |
ARM: dts: Kill off skeleton{64}.dtsi
Remove the usage of skeleton.dtsi in the remaining dts files. It was
deprecated since commit
|
|
|
Martin Blumenstingl
|
c8bfe65fb1 |
ARM: dts: meson8b: ec100: mark the SD card detection GPIO active-low
After commit |
|
|
Martin Blumenstingl
|
bbedc1f1d9 |
ARM: dts: meson8b: Add support for the Endless Mini (EC-100)
The Endless Mini (EC-100) is a grapefruit-sized computer based on the Amlogic Meson8b (S805) SoC which comes in two variants. Both variants have in common: - Amlogic Meson8b (S805) SoC - two USB 2.0 ports on the rear, one one the front (connected to the SoC through an internal hub) - 3.5mm Stereo out and MIC combo port - HDMI and CVBS output - 5V power supply (rated at 3A / 15W) - an internal embedded micro-controller (called "EC") which implements a "breathing" effect for the LED and allows shutting down (powering off) the whole device - 10/100 Mbit/s Ethernet using an IC Plus IP101A/G PHY (note: the website incorrectly lists a Gigabit Ethernet port) - the CPU voltage is regulated using a PWM regulator. The GPL sources of the EC-100 are using a PWM value of 0x1c0000 for 0.86V and a PWM value of 0x00001c for 1.14V. When using the XTAL (24MHz) as input this translates into a PWM period of 1148ns with 0.86V using a duty cycle of 100% and 1.14V using a duty cycle of 0%. The main differences are: - the main indicator for the variant is the RAM size: the "cheaper" variant has 1 GB of RAM, while the more expensive one comes with 2GB - the storage size differs: 24 GB vs 32 GB - the "1 GB RAM" variant has Ethernet connectivity only, while the "2 GB" variant has a Realtek RTL8723BS SDIO chip which adds 802.11b/g/n wifi and Bluetooth 4.0 support Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> |