2 Commits

Author	SHA1	Message	Date
Sricharan Ramabadhran	c17ccefb61	dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller ... The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. The RCG and PLL have a separate register space from the GCC. Also the L3 cache has a separate pll and needs to be scaled along with the CPU. Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> [ Added interconnect related changes ] Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20250811090954.2854440-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-08-11 10:05:20 -05:00
Sivaprakash Murugesan	49bcaef86e	clk: qcom: Add DT bindings for ipq6018 apss clock controller ... Add dt-binding for ipq6018 apss clock controller Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1592800092-20533-4-git-send-email-sivaprak@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-06-22 00:21:59 -07:00