2 Commits

Author	SHA1	Message	Date
Xiaolong Zhang	187e5cd2d1	clk: sprd: add gate for pll clocks ... Some sprd's gate clocks are used to the switch of pll, which need to wait a certain time for stable after being enabled. Signed-off-by: Xiaolong Zhang <xiaolong.zhang@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-2-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-24 19:03:56 -07:00
Chunyan Zhang	cdb09f67a2	clk: sprd: add gate clock support ... Some clocks on the Spreadtrum's SoCs are just simple gates. Add support for those clocks. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2017-12-21 15:00:51 -08:00