Commit Graph

5 Commits

Author SHA1 Message Date
Linus Torvalds 03f76ddff5 - Add support for new AMD family 0x1a models to amd64_edac
- Add an EDAC driver for the AMD VersalNET memory controller which
   reports hw errors from different IP blocks in the fabric using an
   IPC-type transport
 
 - Drop the silly static number of memory controllers in the Intel EDAC
   drivers (skx, i10nm) in favor of a flexible array so that former
   doesn't need to be increased with every new generation which adds more
   memory controllers; along with a proper refactoring
 
 - Add support for two Alder Lake-S SOCs to ie31200_edac
 
 - Add an EDAC driver for ADM Cortex A72 cores, and specifically for
   reporting L1 and L2 cache errors
 
 - Last but not least, the usual fixes, cleanups and improvements all
   over the subsystem
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmjWYXEACgkQEsHwGGHe
 VUqN0g/+KaDOP5caif7/5IJ2fL+9Qv3VvbxucVMS4UgMYBY21V4msfPkuCg8iGes
 zEpFUuEFc2NE6XV9i4JNgYNAR+uffOY4rZb67VSr2rQSVeRvBFHb9aMsXBYssV/r
 XtCfTdJL/bJ7SLk10aWvBM4quLF9BchdoPctNMt5PuN3dtb1dVFi1TkylXKaocRX
 sfu/hOQ0FUbOlYnGTpW+t4TufNcWzC8q9hL4mrbSVHS3XTKk/zQ9PJ8I8f44XqYo
 Bn1JXfAErkgo9rqlmjxU90Lg2G+EV+qwDWs61Ox8q3lzbC+9FOd4WIbD3c9TiTT/
 Io6tx8PvgFUz43lD+XGoCfd87ZI9CbGoVAEEiFWr+HaqL/XVF5NS5GiBNTyxGGaP
 nDzxm1OYQbDEnBfmaWZCMbbd5yCOZ1EZHTgp4VxqJfooU1Ucbct4oPDnERMTNDlv
 UUGDh19BAXwcZ9xpy36AIprppZKOBu0WPjXee9sby5cF+KB57Tbrzd+nm/uZRhHj
 bTkQTfCcs+EPAksG0snGufy4BlfS6UGqx4HkSZ3ITVJQX4x27razsxTDbKDk50jq
 S1cyZlZ5n+mpR0MtC/zNDMB6cxutgAKoqwssVBUiEh9bCaA/tOPqJmoD9Lx2ESDt
 0/QcF1ilBRctunguhDbY8EZKye9gM4WWHW5kxE29PtAzepSdTDo=
 =4oCR
 -----END PGP SIGNATURE-----

Merge tag 'edac_updates_for_v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

Pull EDAC updates from Borislav Petkov:

 - Add support for new AMD family 0x1a models to amd64_edac

 - Add an EDAC driver for the AMD VersalNET memory controller which
   reports hw errors from different IP blocks in the fabric using an
   IPC-type transport

 - Drop the silly static number of memory controllers in the Intel EDAC
   drivers (skx, i10nm) in favor of a flexible array so that former
   doesn't need to be increased with every new generation which adds
   more memory controllers; along with a proper refactoring

 - Add support for two Alder Lake-S SOCs to ie31200_edac

 - Add an EDAC driver for ADM Cortex A72 cores, and specifically for
   reporting L1 and L2 cache errors

 - Last but not least, the usual fixes, cleanups and improvements all
   over the subsystem

* tag 'edac_updates_for_v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras: (23 commits)
  EDAC/versalnet: Return the correct error in mc_probe()
  EDAC/mc_sysfs: Increase legacy channel support to 16
  EDAC/amd64: Add support for AMD family 1Ah-based newer models
  EDAC: Add a driver for the AMD Versal NET DDR controller
  dt-bindings: memory-controllers: Add support for Versal NET EDAC
  RAS: Export log_non_standard_event() to drivers
  cdx: Export Symbols for MCDI RPC and Initialization
  cdx: Split mcdi.h and reorganize headers
  EDAC/skx_common: Use topology_physical_package_id() instead of open coding
  EDAC: Fix wrong executable file modes for C source files
  EDAC/altera: Use dev_fwnode()
  EDAC/skx_common: Remove unused *NUM*_IMC macros
  EDAC/i10nm: Reallocate skx_dev list if preconfigured cnt != runtime cnt
  EDAC/skx_common: Remove redundant upper bound check for res->imc
  EDAC/skx_common: Make skx_dev->imc[] a flexible array
  EDAC/skx_common: Swap memory controller index mapping
  EDAC/skx_common: Move mc_mapping to be a field inside struct skx_imc
  EDAC/{skx_common,skx}: Use configuration data, not global macros
  EDAC/i10nm: Skip DIMM enumeration on a disabled memory controller
  EDAC/ie31200: Add two more Intel Alder Lake-S SoCs for EDAC support
  ...
2025-09-30 11:41:03 -07:00
Shubhrajyoti Datta 54fd6bd42e cdx: Split mcdi.h and reorganize headers
Move bitfield.h from the CDX controller directory to include/linux/cdx to make
them accessible to other drivers.

As part of this refactoring, split mcdi.h into two headers:

- mcdi.h: retains interface-level declarations
- mcdid.h: contains internal definitions and macros

This is in preparation for VersalNET EDAC driver that relies on it.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Nikhil Agarwal <nikhil.agarwal@amd.com>
Link: https://lore.kernel.org/20250908115649.22903-1-shubhrajyoti.datta@amd.com
2025-09-15 15:56:00 +02:00
Thorsten Blum 300a0cfe9f cdx: Fix off-by-one error in cdx_rpmsg_probe()
In cdx_rpmsg_probe(), strscpy() is incorrectly called with the length of
the source string (excluding the NUL terminator) rather than the size of
the destination buffer. This results in one character less being copied
from 'cdx_rpmsg_id_table[0].name' to 'chinfo.name'.

Use the destination buffer size instead to ensure the name is copied
correctly.

Cc: stable <stable@kernel.org>
Fixes: 2a226927d9 ("cdx: add rpmsg communication channel for CDX")
Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
Link: https://lore.kernel.org/r/20250806090512.121260-2-thorsten.blum@linux.dev
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-08-19 12:55:16 +02:00
Rob Herring a436194d0e cdx: Explicitly include correct DT includes
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Nipun Gupta <nipun.gupta@amd.com>
Link: https://lore.kernel.org/r/20230717150355.1749845-1-robh@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-08-04 16:21:20 +02:00
Nipun Gupta 2a226927d9 cdx: add rpmsg communication channel for CDX
RPMsg is used as a transport communication channel. This
change introduces RPMsg driver and integrates it with the
CDX controller.

Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com>
Signed-off-by: Nipun Gupta <nipun.gupta@amd.com>
Reviewed-by: Pieter Jansen van Vuuren <pieter.jansen-van-vuuren@amd.com>
Tested-by: Nikhil Agarwal <nikhil.agarwal@amd.com>
Link: https://lore.kernel.org/r/20230313132636.31850-7-nipun.gupta@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-03-29 12:26:32 +02:00