mirror of https://github.com/torvalds/linux.git
ASoC: spacemit: add i2s support for K1 SoC
Add ASoC platform driver for the SpacemiT K1 SoC full-duplex I2S controller. Co-developer: Jinmei Wei <weijinmei@linux.spacemit.com> Signed-off-by: Jinmei Wei <weijinmei@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://patch.msgid.link/20251017-k1-i2s-v5-2-401ae3775fcd@linux.spacemit.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Troy Mitchell
Mark Brown
parent
73978d274e
commit
fce2174490
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@ -127,6 +127,7 @@ source "sound/soc/renesas/Kconfig"
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source "sound/soc/rockchip/Kconfig"
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source "sound/soc/samsung/Kconfig"
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source "sound/soc/sdca/Kconfig"
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source "sound/soc/spacemit/Kconfig"
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source "sound/soc/spear/Kconfig"
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source "sound/soc/sprd/Kconfig"
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source "sound/soc/starfive/Kconfig"
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@ -70,6 +70,7 @@ obj-$(CONFIG_SND_SOC) += rockchip/
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obj-$(CONFIG_SND_SOC) += samsung/
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obj-$(CONFIG_SND_SOC) += sdca/
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obj-$(CONFIG_SND_SOC) += sof/
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obj-$(CONFIG_SND_SOC) += spacemit/
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obj-$(CONFIG_SND_SOC) += spear/
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obj-$(CONFIG_SND_SOC) += sprd/
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obj-$(CONFIG_SND_SOC) += starfive/
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@ -0,0 +1,16 @@
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# SPDX-License-Identifier: GPL-2.0-only
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menu "SpacemiT"
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depends on COMPILE_TEST || ARCH_SPACEMIT
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depends on HAVE_CLK
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config SND_SOC_K1_I2S
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tristate "K1 I2S Device Driver"
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select SND_SOC_GENERIC_DMAENGINE_PCM
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select CMA
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select DMA_CMA
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help
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Say Y or M if you want to add support for I2S driver for
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K1 I2S controller. The device supports up to maximum of
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2 channels each for play and record.
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endmenu
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@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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# K1 Platform Support
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snd-soc-k1-i2s-y := k1_i2s.o
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obj-$(CONFIG_SND_SOC_K1_I2S) += snd-soc-k1-i2s.o
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@ -0,0 +1,458 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2025 Troy Mitchell <troy.mitchell@linux.spacemit.com> */
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#define SSCR 0x00 /* SPI/I2S top control register */
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#define SSFCR 0x04 /* SPI/I2S FIFO control register */
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#define SSINTEN 0x08 /* SPI/I2S interrupt enable register */
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#define SSDATR 0x10 /* SPI/I2S data register */
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#define SSPSP 0x18 /* SPI/I2S programmable serial protocol control register */
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#define SSRWT 0x24 /* SPI/I2S root control register */
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/* SPI/I2S Work data size, register bits value 0~31 indicated data size 1~32 bits */
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#define SSCR_FIELD_DSS GENMASK(9, 5)
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#define SSCR_DW_8BYTE FIELD_PREP(SSCR_FIELD_DSS, 0x7)
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#define SSCR_DW_16BYTE FIELD_PREP(SSCR_FIELD_DSS, 0xf)
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#define SSCR_DW_18BYTE FIELD_PREP(SSCR_FIELD_DSS, 0x11)
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#define SSCR_DW_32BYTE FIELD_PREP(SSCR_FIELD_DSS, 0x1f)
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#define SSCR_SSE BIT(0) /* SPI/I2S Enable */
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#define SSCR_FRF_PSP GENMASK(2, 1) /* Frame Format*/
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#define SSCR_TRAIL BIT(13) /* Trailing Byte */
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#define SSFCR_FIELD_TFT GENMASK(3, 0) /* TXFIFO Trigger Threshold */
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#define SSFCR_FIELD_RFT GENMASK(8, 5) /* RXFIFO Trigger Threshold */
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#define SSFCR_TSRE BIT(10) /* Transmit Service Request Enable */
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#define SSFCR_RSRE BIT(11) /* Receive Service Request Enable */
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#define SSPSP_FSRT BIT(3) /* Frame Sync Relative Timing Bit */
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#define SSPSP_SFRMP BIT(4) /* Serial Frame Polarity */
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#define SSPSP_FIELD_SFRMWDTH GENMASK(17, 12) /* Serial Frame Width field */
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#define SSRWT_RWOT BIT(0) /* Receive Without Transmit */
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#define SPACEMIT_PCM_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | \
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SNDRV_PCM_RATE_48000)
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#define SPACEMIT_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
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#define SPACEMIT_I2S_PERIOD_SIZE 1024
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struct spacemit_i2s_dev {
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struct device *dev;
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void __iomem *base;
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struct reset_control *reset;
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struct clk *sysclk;
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struct clk *bclk;
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struct clk *sspa_clk;
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struct snd_dmaengine_dai_dma_data capture_dma_data;
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struct snd_dmaengine_dai_dma_data playback_dma_data;
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bool has_capture;
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bool has_playback;
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int dai_fmt;
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int started_count;
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};
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static const struct snd_pcm_hardware spacemit_pcm_hardware = {
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.info = SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_BATCH,
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.formats = SPACEMIT_PCM_FORMATS,
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.rates = SPACEMIT_PCM_RATES,
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.rate_min = SNDRV_PCM_RATE_8000,
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.rate_max = SNDRV_PCM_RATE_192000,
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.channels_min = 1,
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.channels_max = 2,
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.buffer_bytes_max = SPACEMIT_I2S_PERIOD_SIZE * 4 * 4,
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.period_bytes_min = SPACEMIT_I2S_PERIOD_SIZE * 2,
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.period_bytes_max = SPACEMIT_I2S_PERIOD_SIZE * 4,
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.periods_min = 2,
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.periods_max = 4,
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};
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static const struct snd_dmaengine_pcm_config spacemit_dmaengine_pcm_config = {
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.pcm_hardware = &spacemit_pcm_hardware,
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.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
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.chan_names = {"tx", "rx"},
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.prealloc_buffer_size = 32 * 1024,
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};
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static void spacemit_i2s_init(struct spacemit_i2s_dev *i2s)
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{
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u32 sscr_val, sspsp_val, ssfcr_val, ssrwt_val;
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sscr_val = SSCR_TRAIL | SSCR_FRF_PSP;
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ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 5) |
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FIELD_PREP(SSFCR_FIELD_RFT, 5) |
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SSFCR_RSRE | SSFCR_TSRE;
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ssrwt_val = SSRWT_RWOT;
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sspsp_val = SSPSP_SFRMP;
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writel(sscr_val, i2s->base + SSCR);
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writel(ssfcr_val, i2s->base + SSFCR);
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writel(sspsp_val, i2s->base + SSPSP);
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writel(ssrwt_val, i2s->base + SSRWT);
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writel(0, i2s->base + SSINTEN);
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}
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static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct spacemit_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
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struct snd_dmaengine_dai_dma_data *dma_data;
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u32 data_width, data_bits;
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unsigned long bclk_rate;
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u32 val;
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int ret;
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val = readl(i2s->base + SSCR);
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if (val & SSCR_SSE)
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return 0;
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dma_data = &i2s->playback_dma_data;
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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dma_data = &i2s->capture_dma_data;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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data_bits = 8;
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data_width = SSCR_DW_8BYTE;
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dma_data->maxburst = 8;
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dma_data->addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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data_bits = 16;
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data_width = SSCR_DW_16BYTE;
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dma_data->maxburst = 16;
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dma_data->addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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data_bits = 32;
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data_width = SSCR_DW_32BYTE;
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dma_data->maxburst = 32;
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dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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break;
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default:
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dev_dbg(i2s->dev, "unexpected data width type");
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return -EINVAL;
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}
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switch (i2s->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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if (data_bits == 16) {
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data_width = SSCR_DW_32BYTE;
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dma_data->maxburst = 32;
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dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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}
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snd_pcm_hw_constraint_minmax(substream->runtime,
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SNDRV_PCM_HW_PARAM_CHANNELS,
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1, 2);
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snd_pcm_hw_constraint_mask64(substream->runtime,
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SNDRV_PCM_HW_PARAM_FORMAT,
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SNDRV_PCM_FMTBIT_S16_LE);
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break;
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case SND_SOC_DAIFMT_DSP_A:
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case SND_SOC_DAIFMT_DSP_B:
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snd_pcm_hw_constraint_minmax(substream->runtime,
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SNDRV_PCM_HW_PARAM_CHANNELS,
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1, 1);
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snd_pcm_hw_constraint_mask64(substream->runtime,
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SNDRV_PCM_HW_PARAM_FORMAT,
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SNDRV_PCM_FMTBIT_S32_LE);
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break;
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default:
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dev_dbg(i2s->dev, "unexpected format type");
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return -EINVAL;
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}
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val = readl(i2s->base + SSCR);
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val &= ~SSCR_DW_32BYTE;
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val |= data_width;
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writel(val, i2s->base + SSCR);
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bclk_rate = params_channels(params) *
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params_rate(params) *
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data_bits;
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ret = clk_set_rate(i2s->bclk, bclk_rate);
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if (ret)
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return ret;
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return clk_set_rate(i2s->sspa_clk, bclk_rate);
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}
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static int spacemit_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
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unsigned int freq, int dir)
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{
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struct spacemit_i2s_dev *i2s = dev_get_drvdata(cpu_dai->dev);
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if (freq == 0)
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return 0;
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return clk_set_rate(i2s->sysclk, freq);
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}
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static int spacemit_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct spacemit_i2s_dev *i2s = dev_get_drvdata(cpu_dai->dev);
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u32 sspsp_val;
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sspsp_val = readl(i2s->base + SSPSP);
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sspsp_val &= ~SSPSP_FIELD_SFRMWDTH;
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sspsp_val |= SSPSP_FSRT;
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i2s->dai_fmt = fmt;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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sspsp_val |= FIELD_PREP(SSPSP_FIELD_SFRMWDTH, 0x10);
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break;
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case SND_SOC_DAIFMT_DSP_B:
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/* DSP_B: next frame asserted after previous frame end, so clear FSRT */
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sspsp_val &= ~SSPSP_FSRT;
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fallthrough;
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case SND_SOC_DAIFMT_DSP_A:
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sspsp_val |= FIELD_PREP(SSPSP_FIELD_SFRMWDTH, 0x1);
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break;
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default:
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dev_dbg(i2s->dev, "unexpected format type");
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return -EINVAL;
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}
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writel(sspsp_val, i2s->base + SSPSP);
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return 0;
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}
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static int spacemit_i2s_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct spacemit_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
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u32 val;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (!i2s->started_count) {
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val = readl(i2s->base + SSCR);
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val |= SSCR_SSE;
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writel(val, i2s->base + SSCR);
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}
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i2s->started_count++;
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (i2s->started_count)
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i2s->started_count--;
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if (!i2s->started_count) {
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val = readl(i2s->base + SSCR);
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val &= ~SSCR_SSE;
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writel(val, i2s->base + SSCR);
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}
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int spacemit_i2s_dai_probe(struct snd_soc_dai *dai)
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{
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struct spacemit_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
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snd_soc_dai_init_dma_data(dai,
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i2s->has_playback ? &i2s->playback_dma_data : NULL,
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i2s->has_capture ? &i2s->capture_dma_data : NULL);
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reset_control_deassert(i2s->reset);
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spacemit_i2s_init(i2s);
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return 0;
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}
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static int spacemit_i2s_dai_remove(struct snd_soc_dai *dai)
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{
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struct spacemit_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
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reset_control_assert(i2s->reset);
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return 0;
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}
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static const struct snd_soc_dai_ops spacemit_i2s_dai_ops = {
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.probe = spacemit_i2s_dai_probe,
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.remove = spacemit_i2s_dai_remove,
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.hw_params = spacemit_i2s_hw_params,
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.set_sysclk = spacemit_i2s_set_sysclk,
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.set_fmt = spacemit_i2s_set_fmt,
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.trigger = spacemit_i2s_trigger,
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};
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static struct snd_soc_dai_driver spacemit_i2s_dai = {
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.ops = &spacemit_i2s_dai_ops,
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.playback = {
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.channels_min = 1,
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.channels_max = 2,
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.rates = SPACEMIT_PCM_RATES,
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.rate_min = SNDRV_PCM_RATE_8000,
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.rate_max = SNDRV_PCM_RATE_48000,
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.formats = SPACEMIT_PCM_FORMATS,
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},
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.capture = {
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.channels_min = 1,
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.channels_max = 2,
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.rates = SPACEMIT_PCM_RATES,
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.rate_min = SNDRV_PCM_RATE_8000,
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.rate_max = SNDRV_PCM_RATE_48000,
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.formats = SPACEMIT_PCM_FORMATS,
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},
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.symmetric_rate = 1,
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};
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static int spacemit_i2s_init_dai(struct spacemit_i2s_dev *i2s,
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struct snd_soc_dai_driver **dp,
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dma_addr_t addr)
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{
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struct device_node *node = i2s->dev->of_node;
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struct snd_soc_dai_driver *dai;
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struct property *dma_names;
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const char *dma_name;
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of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
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if (!strcmp(dma_name, "tx"))
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i2s->has_playback = true;
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if (!strcmp(dma_name, "rx"))
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i2s->has_capture = true;
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}
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dai = devm_kmemdup(i2s->dev, &spacemit_i2s_dai,
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sizeof(*dai), GFP_KERNEL);
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if (!dai)
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return -ENOMEM;
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if (i2s->has_playback) {
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dai->playback.stream_name = "Playback";
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dai->playback.channels_min = 1;
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dai->playback.channels_max = 2;
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dai->playback.rates = SPACEMIT_PCM_RATES;
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dai->playback.formats = SPACEMIT_PCM_FORMATS;
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i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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i2s->playback_dma_data.maxburst = 32;
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i2s->playback_dma_data.addr = addr;
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}
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if (i2s->has_capture) {
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dai->capture.stream_name = "Capture";
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dai->capture.channels_min = 1;
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dai->capture.channels_max = 2;
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dai->capture.rates = SPACEMIT_PCM_RATES;
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dai->capture.formats = SPACEMIT_PCM_FORMATS;
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|
||||
i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
||||
i2s->capture_dma_data.maxburst = 32;
|
||||
i2s->capture_dma_data.addr = addr;
|
||||
}
|
||||
|
||||
if (dp)
|
||||
*dp = dai;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_component_driver spacemit_i2s_component = {
|
||||
.name = "i2s-k1",
|
||||
.legacy_dai_naming = 1,
|
||||
};
|
||||
|
||||
static int spacemit_i2s_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct snd_soc_dai_driver *dai;
|
||||
struct spacemit_i2s_dev *i2s;
|
||||
struct resource *res;
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
|
||||
if (!i2s)
|
||||
return -ENOMEM;
|
||||
|
||||
i2s->dev = &pdev->dev;
|
||||
|
||||
i2s->sysclk = devm_clk_get_enabled(i2s->dev, "sysclk");
|
||||
if (IS_ERR(i2s->sysclk))
|
||||
return dev_err_probe(i2s->dev, PTR_ERR(i2s->sysclk),
|
||||
"failed to enable sysbase clock\n");
|
||||
|
||||
i2s->bclk = devm_clk_get_enabled(i2s->dev, "bclk");
|
||||
if (IS_ERR(i2s->bclk))
|
||||
return dev_err_probe(i2s->dev, PTR_ERR(i2s->bclk), "failed to enable bit clock\n");
|
||||
|
||||
clk = devm_clk_get_enabled(i2s->dev, "sspa_bus");
|
||||
if (IS_ERR(clk))
|
||||
return dev_err_probe(i2s->dev, PTR_ERR(clk), "failed to enable sspa_bus clock\n");
|
||||
|
||||
i2s->sspa_clk = devm_clk_get_enabled(i2s->dev, "sspa");
|
||||
if (IS_ERR(clk))
|
||||
return dev_err_probe(i2s->dev, PTR_ERR(clk), "failed to enable sspa clock\n");
|
||||
|
||||
i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
||||
if (IS_ERR(i2s->base))
|
||||
return dev_err_probe(i2s->dev, PTR_ERR(i2s->base), "failed to map registers\n");
|
||||
|
||||
i2s->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
|
||||
if (IS_ERR(i2s->reset))
|
||||
return dev_err_probe(i2s->dev, PTR_ERR(i2s->reset),
|
||||
"failed to get reset control");
|
||||
|
||||
dev_set_drvdata(i2s->dev, i2s);
|
||||
|
||||
spacemit_i2s_init_dai(i2s, &dai, res->start + SSDATR);
|
||||
|
||||
ret = devm_snd_soc_register_component(i2s->dev,
|
||||
&spacemit_i2s_component,
|
||||
dai, 1);
|
||||
if (ret)
|
||||
return dev_err_probe(i2s->dev, ret, "failed to register component");
|
||||
|
||||
return devm_snd_dmaengine_pcm_register(&pdev->dev, &spacemit_dmaengine_pcm_config, 0);
|
||||
}
|
||||
|
||||
static const struct of_device_id spacemit_i2s_of_match[] = {
|
||||
{ .compatible = "spacemit,k1-i2s", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, spacemit_i2s_of_match);
|
||||
|
||||
static struct platform_driver spacemit_i2s_driver = {
|
||||
.probe = spacemit_i2s_probe,
|
||||
.driver = {
|
||||
.name = "i2s-k1",
|
||||
.of_match_table = spacemit_i2s_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(spacemit_i2s_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1 SoC");
|
||||
Loading…
Reference in New Issue