mirror of https://github.com/torvalds/linux.git
Merge branch 'icc-misc' into icc-next
This series introduce new ICC drivers for some legacy socs while at it also updates a bit of qcs404 driver which seems to not receive much attention lately. * icc-misc dt-bindings: interconnect: qcom: Add Qualcomm MSM8976 NoC interconnect: qcom: Add MSM8976 interconnect provider driver dt-bindings: interconnect: qcom: Add Qualcomm MSM8937 NoC interconnect: qcom: Add MSM8937 interconnect provider driver interconnect: qcom: qcs404: Mark AP-owned nodes as such interconnect: qcom: qcs404: Add regmaps and more bus descriptions dt-bindings: interconnect: qcom: msm8939: Fix example interconnect: qcom: msm8953: Add ab_coeff dt-bindings: interconnect: qcom: msm8953: Fix 'See also' in description Link: https://lore.kernel.org/all/20240709102728.15349-1-a39.skl@gmail.com/ Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov
commit
f7d27c1cc8
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@ -4,14 +4,14 @@
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$id: http://devicetree.org/schemas/interconnect/qcom,msm8939.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm MSM8939 Network-On-Chip interconnect
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title: Qualcomm MSM8937/MSM8939/MSM8976 Network-On-Chip interconnect
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maintainers:
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- Konrad Dybcio <konradybcio@kernel.org>
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description: |
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The Qualcomm MSM8939 interconnect providers support adjusting the
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bandwidth requirements between the various NoC fabrics.
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description:
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The Qualcomm MSM8937/MSM8939/MSM8976 interconnect providers support
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adjusting the bandwidth requirements between the various NoC fabrics.
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allOf:
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- $ref: qcom,rpm-common.yaml#
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@ -19,9 +19,15 @@ allOf:
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properties:
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compatible:
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enum:
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- qcom,msm8937-bimc
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- qcom,msm8937-pcnoc
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- qcom,msm8937-snoc
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- qcom,msm8939-bimc
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- qcom,msm8939-pcnoc
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- qcom,msm8939-snoc
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- qcom,msm8976-bimc
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- qcom,msm8976-pcnoc
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- qcom,msm8976-snoc
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reg:
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maxItems: 1
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@ -39,7 +45,10 @@ patternProperties:
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properties:
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compatible:
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const: qcom,msm8939-snoc-mm
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enum:
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- qcom,msm8937-snoc-mm
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- qcom,msm8939-snoc-mm
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- qcom,msm8976-snoc-mm
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required:
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- compatible
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@ -60,12 +69,6 @@ examples:
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compatible = "qcom,msm8939-snoc";
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reg = <0x00580000 0x14000>;
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#interconnect-cells = <1>;
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};
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bimc: interconnect@400000 {
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compatible = "qcom,msm8939-bimc";
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reg = <0x00400000 0x62000>;
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#interconnect-cells = <1>;
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snoc_mm: interconnect-snoc {
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compatible = "qcom,msm8939-snoc-mm";
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|
|
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|
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@ -13,8 +13,7 @@ description: |
|
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The Qualcomm MSM8953 interconnect providers support adjusting the
|
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bandwidth requirements between the various NoC fabrics.
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|
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See also:
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- dt-bindings/interconnect/qcom,msm8953.h
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See also: include/dt-bindings/interconnect/qcom,msm8953.h
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|
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properties:
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compatible:
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|
|
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@ -26,6 +26,15 @@ config INTERCONNECT_QCOM_MSM8916
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This is a driver for the Qualcomm Network-on-Chip on msm8916-based
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platforms.
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config INTERCONNECT_QCOM_MSM8937
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tristate "Qualcomm MSM8937 interconnect driver"
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depends on INTERCONNECT_QCOM
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depends on QCOM_SMD_RPM
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select INTERCONNECT_QCOM_SMD_RPM
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help
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This is a driver for the Qualcomm Network-on-Chip on msm8937-based
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platforms.
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|
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config INTERCONNECT_QCOM_MSM8939
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tristate "Qualcomm MSM8939 interconnect driver"
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depends on INTERCONNECT_QCOM
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|
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@ -53,6 +62,15 @@ config INTERCONNECT_QCOM_MSM8974
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This is a driver for the Qualcomm Network-on-Chip on msm8974-based
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platforms.
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config INTERCONNECT_QCOM_MSM8976
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tristate "Qualcomm MSM8976 interconnect driver"
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depends on INTERCONNECT_QCOM
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depends on QCOM_SMD_RPM
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select INTERCONNECT_QCOM_SMD_RPM
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help
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This is a driver for the Qualcomm Network-on-Chip on msm8976-based
|
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platforms.
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|
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config INTERCONNECT_QCOM_MSM8996
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tristate "Qualcomm MSM8996 interconnect driver"
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depends on INTERCONNECT_QCOM
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|
|
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|
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@ -6,9 +6,11 @@ interconnect_qcom-y := icc-common.o
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icc-bcm-voter-objs := bcm-voter.o
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qnoc-msm8909-objs := msm8909.o
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qnoc-msm8916-objs := msm8916.o
|
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qnoc-msm8937-objs := msm8937.o
|
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qnoc-msm8939-objs := msm8939.o
|
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qnoc-msm8953-objs := msm8953.o
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qnoc-msm8974-objs := msm8974.o
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qnoc-msm8976-objs := msm8976.o
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qnoc-msm8996-objs := msm8996.o
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icc-osm-l3-objs := osm-l3.o
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qnoc-qcm2290-objs := qcm2290.o
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|
|
@ -41,9 +43,11 @@ icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o
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obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o
|
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
|
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8937) += qnoc-msm8937.o
|
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) += qnoc-msm8939.o
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8953) += qnoc-msm8953.o
|
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o
|
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8976) += qnoc-msm8976.o
|
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o
|
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obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
|
||||
obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o
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|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1169,6 +1169,7 @@ static const struct qcom_icc_desc msm8953_bimc = {
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.nodes = msm8953_bimc_nodes,
|
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.num_nodes = ARRAY_SIZE(msm8953_bimc_nodes),
|
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.qos_offset = 0x8000,
|
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.ab_coeff = 153,
|
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.regmap_cfg = &msm8953_bimc_regmap_config
|
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};
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|
||||
|
|
@ -1295,6 +1296,7 @@ static const struct qcom_icc_desc msm8953_snoc_mm = {
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.nodes = msm8953_snoc_mm_nodes,
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.num_nodes = ARRAY_SIZE(msm8953_snoc_mm_nodes),
|
||||
.qos_offset = 0x7000,
|
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.ab_coeff = 153,
|
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.regmap_cfg = &msm8953_snoc_regmap_config,
|
||||
};
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -10,6 +10,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
|
||||
#include "icc-rpm.h"
|
||||
|
|
@ -101,6 +102,11 @@ static struct qcom_icc_node mas_apps_proc = {
|
|||
.buswidth = 8,
|
||||
.mas_rpm_id = 0,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_FIXED,
|
||||
.qos.areq_prio = 0,
|
||||
.qos.prio_level = 0,
|
||||
.qos.qos_port = 0,
|
||||
.num_links = ARRAY_SIZE(mas_apps_proc_links),
|
||||
.links = mas_apps_proc_links,
|
||||
};
|
||||
|
|
@ -116,6 +122,11 @@ static struct qcom_icc_node mas_oxili = {
|
|||
.buswidth = 8,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_FIXED,
|
||||
.qos.areq_prio = 0,
|
||||
.qos.prio_level = 0,
|
||||
.qos.qos_port = 2,
|
||||
.num_links = ARRAY_SIZE(mas_oxili_links),
|
||||
.links = mas_oxili_links,
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||||
};
|
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|
|
@ -131,6 +142,11 @@ static struct qcom_icc_node mas_mdp = {
|
|||
.buswidth = 8,
|
||||
.mas_rpm_id = -1,
|
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.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_FIXED,
|
||||
.qos.areq_prio = 0,
|
||||
.qos.prio_level = 1,
|
||||
.qos.qos_port = 4,
|
||||
.num_links = ARRAY_SIZE(mas_mdp_links),
|
||||
.links = mas_mdp_links,
|
||||
};
|
||||
|
|
@ -145,6 +161,10 @@ static struct qcom_icc_node mas_snoc_bimc_1 = {
|
|||
.buswidth = 8,
|
||||
.mas_rpm_id = 76,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
|
||||
.qos.areq_prio = 0,
|
||||
.qos.prio_level = 0,
|
||||
.qos.qos_port = 5,
|
||||
.num_links = ARRAY_SIZE(mas_snoc_bimc_1_links),
|
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.links = mas_snoc_bimc_1_links,
|
||||
};
|
||||
|
|
@ -160,6 +180,11 @@ static struct qcom_icc_node mas_tcu_0 = {
|
|||
.buswidth = 8,
|
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.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_FIXED,
|
||||
.qos.areq_prio = 0,
|
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.qos.prio_level = 2,
|
||||
.qos.qos_port = 6,
|
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.num_links = ARRAY_SIZE(mas_tcu_0_links),
|
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.links = mas_tcu_0_links,
|
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};
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|
|
@ -174,6 +199,8 @@ static struct qcom_icc_node mas_spdm = {
|
|||
.buswidth = 4,
|
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.mas_rpm_id = -1,
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.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
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.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
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.num_links = ARRAY_SIZE(mas_spdm_links),
|
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.links = mas_spdm_links,
|
||||
};
|
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|
|
@ -231,6 +258,11 @@ static struct qcom_icc_node mas_crypto = {
|
|||
.buswidth = 8,
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.mas_rpm_id = 23,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
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.qos.qos_mode = NOC_QOS_MODE_FIXED,
|
||||
.qos.areq_prio = 1,
|
||||
.qos.prio_level = 1,
|
||||
.qos.qos_port = 0,
|
||||
.num_links = ARRAY_SIZE(mas_crypto_links),
|
||||
.links = mas_crypto_links,
|
||||
};
|
||||
|
|
@ -287,6 +319,11 @@ static struct qcom_icc_node mas_qpic = {
|
|||
.buswidth = 4,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_FIXED,
|
||||
.qos.areq_prio = 1,
|
||||
.qos.prio_level = 1,
|
||||
.qos.qos_port = 14,
|
||||
.num_links = ARRAY_SIZE(mas_qpic_links),
|
||||
.links = mas_qpic_links,
|
||||
};
|
||||
|
|
@ -301,6 +338,11 @@ static struct qcom_icc_node mas_qdss_bam = {
|
|||
.buswidth = 4,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_FIXED,
|
||||
.qos.areq_prio = 1,
|
||||
.qos.prio_level = 1,
|
||||
.qos.qos_port = 1,
|
||||
.num_links = ARRAY_SIZE(mas_qdss_bam_links),
|
||||
.links = mas_qdss_bam_links,
|
||||
};
|
||||
|
|
@ -348,6 +390,11 @@ static struct qcom_icc_node mas_qdss_etr = {
|
|||
.buswidth = 8,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_FIXED,
|
||||
.qos.areq_prio = 1,
|
||||
.qos.prio_level = 1,
|
||||
.qos.qos_port = 0,
|
||||
.num_links = ARRAY_SIZE(mas_qdss_etr_links),
|
||||
.links = mas_qdss_etr_links,
|
||||
};
|
||||
|
|
@ -363,6 +410,11 @@ static struct qcom_icc_node mas_emac = {
|
|||
.buswidth = 8,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_FIXED,
|
||||
.qos.areq_prio = 1,
|
||||
.qos.prio_level = 1,
|
||||
.qos.qos_port = 17,
|
||||
.num_links = ARRAY_SIZE(mas_emac_links),
|
||||
.links = mas_emac_links,
|
||||
};
|
||||
|
|
@ -378,6 +430,11 @@ static struct qcom_icc_node mas_pcie = {
|
|||
.buswidth = 8,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_FIXED,
|
||||
.qos.areq_prio = 1,
|
||||
.qos.prio_level = 1,
|
||||
.qos.qos_port = 8,
|
||||
.num_links = ARRAY_SIZE(mas_pcie_links),
|
||||
.links = mas_pcie_links,
|
||||
};
|
||||
|
|
@ -393,6 +450,11 @@ static struct qcom_icc_node mas_usb3 = {
|
|||
.buswidth = 8,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_FIXED,
|
||||
.qos.areq_prio = 1,
|
||||
.qos.prio_level = 1,
|
||||
.qos.qos_port = 16,
|
||||
.num_links = ARRAY_SIZE(mas_usb3_links),
|
||||
.links = mas_usb3_links,
|
||||
};
|
||||
|
|
@ -491,6 +553,8 @@ static struct qcom_icc_node pcnoc_s_2 = {
|
|||
.buswidth = 4,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
.num_links = ARRAY_SIZE(pcnoc_s_2_links),
|
||||
.links = pcnoc_s_2_links,
|
||||
};
|
||||
|
|
@ -626,6 +690,8 @@ static struct qcom_icc_node qdss_int = {
|
|||
.buswidth = 8,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
.num_links = ARRAY_SIZE(qdss_int_links),
|
||||
.links = qdss_int_links,
|
||||
};
|
||||
|
|
@ -704,6 +770,8 @@ static struct qcom_icc_node slv_spdm = {
|
|||
.buswidth = 4,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node slv_pdm = {
|
||||
|
|
@ -752,6 +820,8 @@ static struct qcom_icc_node slv_disp_ss_cfg = {
|
|||
.buswidth = 4,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node slv_gpu_cfg = {
|
||||
|
|
@ -760,6 +830,8 @@ static struct qcom_icc_node slv_gpu_cfg = {
|
|||
.buswidth = 4,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node slv_blsp_1 = {
|
||||
|
|
@ -784,6 +856,8 @@ static struct qcom_icc_node slv_pcie = {
|
|||
.buswidth = 4,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node slv_ethernet = {
|
||||
|
|
@ -792,6 +866,8 @@ static struct qcom_icc_node slv_ethernet = {
|
|||
.buswidth = 4,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node slv_blsp_2 = {
|
||||
|
|
@ -816,6 +892,8 @@ static struct qcom_icc_node slv_tcu = {
|
|||
.buswidth = 8,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node slv_pmic_arb = {
|
||||
|
|
@ -894,6 +972,8 @@ static struct qcom_icc_node slv_kpss_ahb = {
|
|||
.buswidth = 4,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node slv_wcss = {
|
||||
|
|
@ -954,6 +1034,8 @@ static struct qcom_icc_node slv_cats_0 = {
|
|||
.buswidth = 16,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node slv_cats_1 = {
|
||||
|
|
@ -962,6 +1044,8 @@ static struct qcom_icc_node slv_cats_1 = {
|
|||
.buswidth = 8,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node slv_lpass = {
|
||||
|
|
@ -970,6 +1054,8 @@ static struct qcom_icc_node slv_lpass = {
|
|||
.buswidth = 4,
|
||||
.mas_rpm_id = -1,
|
||||
.slv_rpm_id = -1,
|
||||
.qos.ap_owned = true,
|
||||
.qos.qos_mode = NOC_QOS_MODE_INVALID,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const qcs404_bimc_nodes[] = {
|
||||
|
|
@ -982,10 +1068,22 @@ static struct qcom_icc_node * const qcs404_bimc_nodes[] = {
|
|||
[SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config qcs404_bimc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x80000,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc qcs404_bimc = {
|
||||
.bus_clk_desc = &bimc_clk,
|
||||
.type = QCOM_ICC_BIMC,
|
||||
.nodes = qcs404_bimc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
|
||||
.bus_clk_desc = &bimc_clk,
|
||||
.regmap_cfg = &qcs404_bimc_regmap_config,
|
||||
.qos_offset = 0x8000,
|
||||
.ab_coeff = 153,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = {
|
||||
|
|
@ -1037,10 +1135,22 @@ static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = {
|
|||
[SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc,
|
||||
};
|
||||
|
||||
static const struct regmap_config qcs404_pcnoc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x15080,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc qcs404_pcnoc = {
|
||||
.bus_clk_desc = &bus_0_clk,
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = qcs404_pcnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
|
||||
.bus_clk_desc = &bus_0_clk,
|
||||
.qos_offset = 0x7000,
|
||||
.keep_alive = true,
|
||||
.regmap_cfg = &qcs404_pcnoc_regmap_config,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const qcs404_snoc_nodes[] = {
|
||||
|
|
@ -1066,10 +1176,21 @@ static struct qcom_icc_node * const qcs404_snoc_nodes[] = {
|
|||
[SLAVE_LPASS] = &slv_lpass,
|
||||
};
|
||||
|
||||
static const struct regmap_config qcs404_snoc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x23080,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc qcs404_snoc = {
|
||||
.bus_clk_desc = &bus_1_clk,
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = qcs404_snoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
|
||||
.bus_clk_desc = &bus_1_clk,
|
||||
.qos_offset = 0x11000,
|
||||
.regmap_cfg = &qcs404_snoc_regmap_config,
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,93 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Qualcomm MSM8937 interconnect IDs
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8937_H
|
||||
#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8937_H
|
||||
|
||||
/* BIMC fabric */
|
||||
#define MAS_APPS_PROC 0
|
||||
#define MAS_OXILI 1
|
||||
#define MAS_SNOC_BIMC_0 2
|
||||
#define MAS_SNOC_BIMC_2 3
|
||||
#define MAS_SNOC_BIMC_1 4
|
||||
#define MAS_TCU_0 5
|
||||
#define SLV_EBI 6
|
||||
#define SLV_BIMC_SNOC 7
|
||||
|
||||
/* PCNOC fabric */
|
||||
#define MAS_SPDM 0
|
||||
#define MAS_BLSP_1 1
|
||||
#define MAS_BLSP_2 2
|
||||
#define MAS_USB_HS1 3
|
||||
#define MAS_XI_USB_HS1 4
|
||||
#define MAS_CRYPTO 5
|
||||
#define MAS_SDCC_1 6
|
||||
#define MAS_SDCC_2 7
|
||||
#define MAS_SNOC_PCNOC 8
|
||||
#define PCNOC_M_0 9
|
||||
#define PCNOC_M_1 10
|
||||
#define PCNOC_INT_0 11
|
||||
#define PCNOC_INT_1 12
|
||||
#define PCNOC_INT_2 13
|
||||
#define PCNOC_INT_3 14
|
||||
#define PCNOC_S_0 15
|
||||
#define PCNOC_S_1 16
|
||||
#define PCNOC_S_2 17
|
||||
#define PCNOC_S_3 18
|
||||
#define PCNOC_S_4 19
|
||||
#define PCNOC_S_6 20
|
||||
#define PCNOC_S_7 21
|
||||
#define PCNOC_S_8 22
|
||||
#define SLV_SDCC_2 23
|
||||
#define SLV_SPDM 24
|
||||
#define SLV_PDM 25
|
||||
#define SLV_PRNG 26
|
||||
#define SLV_TCSR 27
|
||||
#define SLV_SNOC_CFG 28
|
||||
#define SLV_MESSAGE_RAM 29
|
||||
#define SLV_CAMERA_SS_CFG 30
|
||||
#define SLV_DISP_SS_CFG 31
|
||||
#define SLV_VENUS_CFG 32
|
||||
#define SLV_GPU_CFG 33
|
||||
#define SLV_TLMM 34
|
||||
#define SLV_BLSP_1 35
|
||||
#define SLV_BLSP_2 36
|
||||
#define SLV_PMIC_ARB 37
|
||||
#define SLV_SDCC_1 38
|
||||
#define SLV_CRYPTO_0_CFG 39
|
||||
#define SLV_USB_HS 40
|
||||
#define SLV_TCU 41
|
||||
#define SLV_PCNOC_SNOC 42
|
||||
|
||||
/* SNOC fabric */
|
||||
#define MAS_QDSS_BAM 0
|
||||
#define MAS_BIMC_SNOC 1
|
||||
#define MAS_PCNOC_SNOC 2
|
||||
#define MAS_QDSS_ETR 3
|
||||
#define QDSS_INT 4
|
||||
#define SNOC_INT_0 5
|
||||
#define SNOC_INT_1 6
|
||||
#define SNOC_INT_2 7
|
||||
#define SLV_KPSS_AHB 8
|
||||
#define SLV_WCSS 9
|
||||
#define SLV_SNOC_BIMC_1 10
|
||||
#define SLV_IMEM 11
|
||||
#define SLV_SNOC_PCNOC 12
|
||||
#define SLV_QDSS_STM 13
|
||||
#define SLV_CATS_1 14
|
||||
#define SLV_LPASS 15
|
||||
|
||||
/* SNOC-MM fabric */
|
||||
#define MAS_JPEG 0
|
||||
#define MAS_MDP 1
|
||||
#define MAS_VENUS 2
|
||||
#define MAS_VFE0 3
|
||||
#define MAS_VFE1 4
|
||||
#define MAS_CPP 5
|
||||
#define SLV_SNOC_BIMC_0 6
|
||||
#define SLV_SNOC_BIMC_2 7
|
||||
#define SLV_CATS_0 8
|
||||
|
||||
#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8937_H */
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Qualcomm MSM8976 interconnect IDs
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8976_H
|
||||
#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8976_H
|
||||
|
||||
/* BIMC fabric */
|
||||
#define MAS_APPS_PROC 0
|
||||
#define MAS_SMMNOC_BIMC 1
|
||||
#define MAS_SNOC_BIMC 2
|
||||
#define MAS_TCU_0 3
|
||||
#define SLV_EBI 4
|
||||
#define SLV_BIMC_SNOC 5
|
||||
|
||||
/* PCNOC fabric */
|
||||
#define MAS_USB_HS2 0
|
||||
#define MAS_BLSP_1 1
|
||||
#define MAS_USB_HS1 2
|
||||
#define MAS_BLSP_2 3
|
||||
#define MAS_CRYPTO 4
|
||||
#define MAS_SDCC_1 5
|
||||
#define MAS_SDCC_2 6
|
||||
#define MAS_SDCC_3 7
|
||||
#define MAS_SNOC_PCNOC 8
|
||||
#define MAS_LPASS_AHB 9
|
||||
#define MAS_SPDM 10
|
||||
#define MAS_DEHR 11
|
||||
#define MAS_XM_USB_HS1 12
|
||||
#define PCNOC_M_0 13
|
||||
#define PCNOC_M_1 14
|
||||
#define PCNOC_INT_0 15
|
||||
#define PCNOC_INT_1 16
|
||||
#define PCNOC_INT_2 17
|
||||
#define PCNOC_S_1 18
|
||||
#define PCNOC_S_2 19
|
||||
#define PCNOC_S_3 20
|
||||
#define PCNOC_S_4 21
|
||||
#define PCNOC_S_8 22
|
||||
#define PCNOC_S_9 23
|
||||
#define SLV_TCSR 24
|
||||
#define SLV_TLMM 25
|
||||
#define SLV_CRYPTO_0_CFG 26
|
||||
#define SLV_MESSAGE_RAM 27
|
||||
#define SLV_PDM 28
|
||||
#define SLV_PRNG 29
|
||||
#define SLV_PMIC_ARB 30
|
||||
#define SLV_SNOC_CFG 31
|
||||
#define SLV_DCC_CFG 32
|
||||
#define SLV_CAMERA_SS_CFG 33
|
||||
#define SLV_DISP_SS_CFG 34
|
||||
#define SLV_VENUS_CFG 35
|
||||
#define SLV_SDCC_1 36
|
||||
#define SLV_BLSP_1 37
|
||||
#define SLV_USB_HS 38
|
||||
#define SLV_SDCC_3 39
|
||||
#define SLV_SDCC_2 40
|
||||
#define SLV_GPU_CFG 41
|
||||
#define SLV_USB_HS2 42
|
||||
#define SLV_BLSP_2 43
|
||||
#define SLV_PCNOC_SNOC 44
|
||||
|
||||
/* SNOC fabric */
|
||||
#define MAS_QDSS_BAM 0
|
||||
#define MAS_BIMC_SNOC 1
|
||||
#define MAS_PCNOC_SNOC 2
|
||||
#define MAS_QDSS_ETR 3
|
||||
#define MAS_LPASS_PROC 4
|
||||
#define MAS_IPA 5
|
||||
#define QDSS_INT 6
|
||||
#define SNOC_INT_0 7
|
||||
#define SNOC_INT_1 8
|
||||
#define SNOC_INT_2 9
|
||||
#define SLV_KPSS_AHB 10
|
||||
#define SLV_SNOC_BIMC 11
|
||||
#define SLV_IMEM 12
|
||||
#define SLV_SNOC_PCNOC 13
|
||||
#define SLV_QDSS_STM 14
|
||||
#define SLV_CATS_0 15
|
||||
#define SLV_CATS_1 16
|
||||
#define SLV_LPASS 17
|
||||
|
||||
/* SNOC-MM fabric */
|
||||
#define MAS_JPEG 0
|
||||
#define MAS_OXILI 1
|
||||
#define MAS_MDP0 2
|
||||
#define MAS_MDP1 3
|
||||
#define MAS_VENUS_0 4
|
||||
#define MAS_VENUS_1 5
|
||||
#define MAS_VFE_0 6
|
||||
#define MAS_VFE_1 7
|
||||
#define MAS_CPP 8
|
||||
#define MM_INT_0 9
|
||||
#define SLV_SMMNOC_BIMC 10
|
||||
|
||||
#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8976_H */
|
||||
Loading…
Reference in New Issue