mirror of https://github.com/torvalds/linux.git
Merge branch 'pci/controller/brcmstb'
- Disable advertising ASPM L0s support correctly (Jim Quinlan) - Add a panic/die handler to print diagnostic info in case PCIe caused an unrecoverable abort (Jim Quinlan) * pci/controller/brcmstb: PCI: brcmstb: Add panic/die handler to driver PCI: brcmstb: Add a way to indicate if PCIe bridge is active PCI: brcmstb: Fix disabling L0s capability
This commit is contained in:
Bjorn Helgaas
commit
f4620f6216
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@ -14,15 +14,18 @@
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqchip/irq-msi-lib.h>
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#include <linux/irqdomain.h>
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#include <linux/kdebug.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/notifier.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/panic_notifier.h>
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#include <linux/pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/printk.h>
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@ -30,7 +33,9 @@
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#include <linux/reset.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/string_choices.h>
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#include <linux/types.h>
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#include "../pci.h"
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@ -48,7 +53,6 @@
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#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
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#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK 0x1f0
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#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
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#define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8
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#define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8
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@ -155,8 +159,40 @@
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#define MSI_INT_MASK_SET 0x10
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#define MSI_INT_MASK_CLR 0x14
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/* Error report registers */
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#define PCIE_OUTB_ERR_TREAT 0x6000
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#define PCIE_OUTB_ERR_TREAT_CONFIG 0x1
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#define PCIE_OUTB_ERR_TREAT_MEM 0x2
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#define PCIE_OUTB_ERR_VALID 0x6004
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#define PCIE_OUTB_ERR_CLEAR 0x6008
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#define PCIE_OUTB_ERR_ACC_INFO 0x600c
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#define PCIE_OUTB_ERR_ACC_INFO_CFG_ERR BIT(0)
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#define PCIE_OUTB_ERR_ACC_INFO_MEM_ERR BIT(1)
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#define PCIE_OUTB_ERR_ACC_INFO_TYPE_64 BIT(2)
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#define PCIE_OUTB_ERR_ACC_INFO_DIR_WRITE BIT(4)
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#define PCIE_OUTB_ERR_ACC_INFO_BYTE_LANES 0xff00
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#define PCIE_OUTB_ERR_ACC_ADDR 0x6010
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#define PCIE_OUTB_ERR_ACC_ADDR_BUS 0xff00000
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#define PCIE_OUTB_ERR_ACC_ADDR_DEV 0xf8000
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#define PCIE_OUTB_ERR_ACC_ADDR_FUNC 0x7000
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#define PCIE_OUTB_ERR_ACC_ADDR_REG 0xfff
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#define PCIE_OUTB_ERR_CFG_CAUSE 0x6014
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#define PCIE_OUTB_ERR_CFG_CAUSE_TIMEOUT BIT(6)
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#define PCIE_OUTB_ERR_CFG_CAUSE_ABORT BIT(5)
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#define PCIE_OUTB_ERR_CFG_CAUSE_UNSUPP_REQ BIT(4)
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#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_TIMEOUT BIT(2)
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#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_DISABLED BIT(1)
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#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_64BIT BIT(0)
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#define PCIE_OUTB_ERR_MEM_ADDR_LO 0x6018
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#define PCIE_OUTB_ERR_MEM_ADDR_HI 0x601c
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#define PCIE_OUTB_ERR_MEM_CAUSE 0x6020
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#define PCIE_OUTB_ERR_MEM_CAUSE_TIMEOUT BIT(6)
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#define PCIE_OUTB_ERR_MEM_CAUSE_ABORT BIT(5)
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#define PCIE_OUTB_ERR_MEM_CAUSE_UNSUPP_REQ BIT(4)
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#define PCIE_OUTB_ERR_MEM_CAUSE_ACC_DISABLED BIT(1)
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#define PCIE_OUTB_ERR_MEM_CAUSE_BAD_ADDR BIT(0)
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#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
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#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
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#define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
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#define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
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@ -259,6 +295,7 @@ struct pcie_cfg_data {
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int (*perst_set)(struct brcm_pcie *pcie, u32 val);
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int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
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int (*post_setup)(struct brcm_pcie *pcie);
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bool has_err_report;
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};
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struct subdev_regulators {
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@ -303,6 +340,10 @@ struct brcm_pcie {
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struct subdev_regulators *sr;
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bool ep_wakeup_capable;
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const struct pcie_cfg_data *cfg;
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bool bridge_in_reset;
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struct notifier_block die_notifier;
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struct notifier_block panic_notifier;
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spinlock_t bridge_lock;
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};
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static inline bool is_bmips(const struct brcm_pcie *pcie)
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@ -310,6 +351,24 @@ static inline bool is_bmips(const struct brcm_pcie *pcie)
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return pcie->cfg->soc_base == BCM7435 || pcie->cfg->soc_base == BCM7425;
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}
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static int brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val)
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{
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unsigned long flags;
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int ret;
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if (pcie->cfg->has_err_report)
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spin_lock_irqsave(&pcie->bridge_lock, flags);
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ret = pcie->cfg->bridge_sw_init_set(pcie, val);
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/* If we fail, assume the bridge is in reset (off) */
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pcie->bridge_in_reset = ret ? true : val;
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if (pcie->cfg->has_err_report)
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spin_unlock_irqrestore(&pcie->bridge_lock, flags);
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return ret;
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}
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/*
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* This is to convert the size of the inbound "BAR" region to the
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* non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
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@ -1075,13 +1134,13 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
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void __iomem *base = pcie->base;
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struct pci_host_bridge *bridge;
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struct resource_entry *entry;
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u32 tmp, burst, aspm_support, num_lanes, num_lanes_cap;
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u32 tmp, burst, num_lanes, num_lanes_cap;
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u8 num_out_wins = 0;
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int num_inbound_wins = 0;
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int memc, ret;
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/* Reset the bridge */
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ret = pcie->cfg->bridge_sw_init_set(pcie, 1);
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ret = brcm_pcie_bridge_sw_init_set(pcie, 1);
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if (ret)
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return ret;
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@ -1097,7 +1156,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
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usleep_range(100, 200);
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/* Take the bridge out of reset */
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ret = pcie->cfg->bridge_sw_init_set(pcie, 0);
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ret = brcm_pcie_bridge_sw_init_set(pcie, 0);
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if (ret)
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return ret;
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@ -1175,12 +1234,9 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
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/* Don't advertise L0s capability if 'aspm-no-l0s' */
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aspm_support = PCIE_LINK_STATE_L1;
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if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
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aspm_support |= PCIE_LINK_STATE_L0S;
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tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
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u32p_replace_bits(&tmp, aspm_support,
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PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
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if (of_property_read_bool(pcie->np, "aspm-no-l0s"))
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tmp &= ~PCI_EXP_LNKCAP_ASPM_L0S;
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writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
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/* 'tmp' still holds the contents of PRIV1_LINK_CAPABILITY */
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@ -1565,7 +1621,7 @@ static int brcm_pcie_turn_off(struct brcm_pcie *pcie)
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if (!(pcie->cfg->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN))
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/* Shutdown PCIe bridge */
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ret = pcie->cfg->bridge_sw_init_set(pcie, 1);
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ret = brcm_pcie_bridge_sw_init_set(pcie, 1);
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return ret;
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}
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@ -1653,7 +1709,9 @@ static int brcm_pcie_resume_noirq(struct device *dev)
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goto err_reset;
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/* Take bridge out of reset so we can access the SERDES reg */
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pcie->cfg->bridge_sw_init_set(pcie, 0);
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ret = brcm_pcie_bridge_sw_init_set(pcie, 0);
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if (ret)
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goto err_reset;
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/* SERDES_IDDQ = 0 */
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tmp = readl(base + HARD_DEBUG(pcie));
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@ -1707,6 +1765,119 @@ static int brcm_pcie_resume_noirq(struct device *dev)
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return ret;
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}
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/* Dump out PCIe errors on die or panic */
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static int brcm_pcie_dump_err(struct brcm_pcie *pcie,
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const char *type)
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{
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void __iomem *base = pcie->base;
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int i, is_cfg_err, is_mem_err, lanes;
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const char *width_str, *direction_str;
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u32 info, cfg_addr, cfg_cause, mem_cause, lo, hi;
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
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unsigned long flags;
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char lanes_str[9];
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spin_lock_irqsave(&pcie->bridge_lock, flags);
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/* Don't access registers when the bridge is off */
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if (pcie->bridge_in_reset || readl(base + PCIE_OUTB_ERR_VALID) == 0) {
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spin_unlock_irqrestore(&pcie->bridge_lock, flags);
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return NOTIFY_DONE;
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}
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/* Read all necessary registers so we can release the spinlock ASAP */
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info = readl(base + PCIE_OUTB_ERR_ACC_INFO);
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is_cfg_err = !!(info & PCIE_OUTB_ERR_ACC_INFO_CFG_ERR);
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is_mem_err = !!(info & PCIE_OUTB_ERR_ACC_INFO_MEM_ERR);
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if (is_cfg_err) {
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cfg_addr = readl(base + PCIE_OUTB_ERR_ACC_ADDR);
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cfg_cause = readl(base + PCIE_OUTB_ERR_CFG_CAUSE);
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}
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if (is_mem_err) {
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mem_cause = readl(base + PCIE_OUTB_ERR_MEM_CAUSE);
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lo = readl(base + PCIE_OUTB_ERR_MEM_ADDR_LO);
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hi = readl(base + PCIE_OUTB_ERR_MEM_ADDR_HI);
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}
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/* We've got all of the info, clear the error */
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writel(1, base + PCIE_OUTB_ERR_CLEAR);
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spin_unlock_irqrestore(&pcie->bridge_lock, flags);
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dev_err(pcie->dev, "reporting PCIe info which may be related to %s error\n",
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type);
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width_str = (info & PCIE_OUTB_ERR_ACC_INFO_TYPE_64) ? "64bit" : "32bit";
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direction_str = str_read_write(!(info & PCIE_OUTB_ERR_ACC_INFO_DIR_WRITE));
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lanes = FIELD_GET(PCIE_OUTB_ERR_ACC_INFO_BYTE_LANES, info);
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for (i = 0, lanes_str[8] = 0; i < 8; i++)
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lanes_str[i] = (lanes & (1 << i)) ? '1' : '0';
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if (is_cfg_err) {
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int bus = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_BUS, cfg_addr);
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int dev = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_DEV, cfg_addr);
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int func = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_FUNC, cfg_addr);
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int reg = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_REG, cfg_addr);
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dev_err(pcie->dev, "Error: CFG Acc, %s, %s (%04x:%02x:%02x.%d) reg=0x%x, lanes=%s\n",
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width_str, direction_str, bridge->domain_nr, bus, dev,
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func, reg, lanes_str);
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dev_err(pcie->dev, " Type: TO=%d Abt=%d UnsupReq=%d AccTO=%d AccDsbld=%d Acc64bit=%d\n",
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!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_TIMEOUT),
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!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_ABORT),
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!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_UNSUPP_REQ),
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!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_TIMEOUT),
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!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_DISABLED),
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!!(cfg_cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_64BIT));
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}
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if (is_mem_err) {
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u64 addr = ((u64)hi << 32) | (u64)lo;
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dev_err(pcie->dev, "Error: Mem Acc, %s, %s, @0x%llx, lanes=%s\n",
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width_str, direction_str, addr, lanes_str);
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dev_err(pcie->dev, " Type: TO=%d Abt=%d UnsupReq=%d AccDsble=%d BadAddr=%d\n",
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!!(mem_cause & PCIE_OUTB_ERR_MEM_CAUSE_TIMEOUT),
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!!(mem_cause & PCIE_OUTB_ERR_MEM_CAUSE_ABORT),
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!!(mem_cause & PCIE_OUTB_ERR_MEM_CAUSE_UNSUPP_REQ),
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!!(mem_cause & PCIE_OUTB_ERR_MEM_CAUSE_ACC_DISABLED),
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!!(mem_cause & PCIE_OUTB_ERR_MEM_CAUSE_BAD_ADDR));
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}
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return NOTIFY_DONE;
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}
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static int brcm_pcie_die_notify_cb(struct notifier_block *self,
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unsigned long v, void *p)
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{
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struct brcm_pcie *pcie =
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container_of(self, struct brcm_pcie, die_notifier);
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return brcm_pcie_dump_err(pcie, "Die");
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}
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static int brcm_pcie_panic_notify_cb(struct notifier_block *self,
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unsigned long v, void *p)
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{
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struct brcm_pcie *pcie =
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container_of(self, struct brcm_pcie, panic_notifier);
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return brcm_pcie_dump_err(pcie, "Panic");
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}
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static void brcm_register_die_notifiers(struct brcm_pcie *pcie)
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{
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pcie->panic_notifier.notifier_call = brcm_pcie_panic_notify_cb;
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atomic_notifier_chain_register(&panic_notifier_list,
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&pcie->panic_notifier);
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pcie->die_notifier.notifier_call = brcm_pcie_die_notify_cb;
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register_die_notifier(&pcie->die_notifier);
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}
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static void brcm_unregister_die_notifiers(struct brcm_pcie *pcie)
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{
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unregister_die_notifier(&pcie->die_notifier);
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atomic_notifier_chain_unregister(&panic_notifier_list,
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&pcie->panic_notifier);
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}
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static void __brcm_pcie_remove(struct brcm_pcie *pcie)
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{
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brcm_msi_remove(pcie);
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@ -1725,6 +1896,9 @@ static void brcm_pcie_remove(struct platform_device *pdev)
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pci_stop_root_bus(bridge->bus);
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pci_remove_root_bus(bridge->bus);
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if (pcie->cfg->has_err_report)
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brcm_unregister_die_notifiers(pcie);
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__brcm_pcie_remove(pcie);
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}
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@ -1825,6 +1999,7 @@ static const struct pcie_cfg_data bcm7216_cfg = {
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.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
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.has_phy = true,
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.num_inbound_wins = 3,
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.has_err_report = true,
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};
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static const struct pcie_cfg_data bcm7712_cfg = {
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@ -1921,7 +2096,10 @@ static int brcm_pcie_probe(struct platform_device *pdev)
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "could not enable clock\n");
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pcie->cfg->bridge_sw_init_set(pcie, 0);
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ret = brcm_pcie_bridge_sw_init_set(pcie, 0);
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if (ret)
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return dev_err_probe(&pdev->dev, ret,
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"could not de-assert bridge reset\n");
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if (pcie->swinit_reset) {
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ret = reset_control_assert(pcie->swinit_reset);
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@ -1996,6 +2174,11 @@ static int brcm_pcie_probe(struct platform_device *pdev)
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return ret;
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}
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if (pcie->cfg->has_err_report) {
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spin_lock_init(&pcie->bridge_lock);
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brcm_register_die_notifiers(pcie);
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}
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return 0;
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fail:
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