mirror of https://github.com/torvalds/linux.git
ntb_hw_amd: Update amd_ntb_get_link_status to support latest generation secondary topology
In the NTB secondary topology configuration of the latest generation, the device behaves like an endpoint. Hence, add endpoint support and update amd_ntb_get_link_status to accommodate endpoint devices. Co-developed-by: Sanath S <Sanath.S@amd.com> Signed-off-by: Sanath S <Sanath.S@amd.com> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
This commit is contained in:
parent
8f5ae30d69
commit
f0c260f175
|
|
@ -197,13 +197,22 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
|
||||||
|
|
||||||
static int amd_ntb_get_link_status(struct amd_ntb_dev *ndev)
|
static int amd_ntb_get_link_status(struct amd_ntb_dev *ndev)
|
||||||
{
|
{
|
||||||
struct pci_dev *pdev = NULL;
|
struct pci_dev *pdev = ndev->ntb.pdev;
|
||||||
struct pci_dev *pci_swds = NULL;
|
struct pci_dev *pci_swds = NULL;
|
||||||
struct pci_dev *pci_swus = NULL;
|
struct pci_dev *pci_swus = NULL;
|
||||||
u32 stat;
|
u32 stat;
|
||||||
int rc;
|
int rc;
|
||||||
|
|
||||||
if (ndev->ntb.topo == NTB_TOPO_SEC) {
|
if (ndev->ntb.topo == NTB_TOPO_SEC) {
|
||||||
|
if (ndev->dev_data->is_endpoint) {
|
||||||
|
rc = pcie_capability_read_dword(pdev, PCI_EXP_LNKCTL, &stat);
|
||||||
|
if (rc)
|
||||||
|
return rc;
|
||||||
|
|
||||||
|
ndev->lnk_sta = stat;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
/* Locate the pointer to Downstream Switch for this device */
|
/* Locate the pointer to Downstream Switch for this device */
|
||||||
pci_swds = pci_upstream_bridge(ndev->ntb.pdev);
|
pci_swds = pci_upstream_bridge(ndev->ntb.pdev);
|
||||||
if (pci_swds) {
|
if (pci_swds) {
|
||||||
|
|
@ -1311,6 +1320,11 @@ static const struct ntb_dev_data dev_data[] = {
|
||||||
.mw_count = 2,
|
.mw_count = 2,
|
||||||
.mw_idx = 2,
|
.mw_idx = 2,
|
||||||
},
|
},
|
||||||
|
{ /* for device 0x17d7 */
|
||||||
|
.mw_count = 2,
|
||||||
|
.mw_idx = 2,
|
||||||
|
.is_endpoint = true,
|
||||||
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct pci_device_id amd_ntb_pci_tbl[] = {
|
static const struct pci_device_id amd_ntb_pci_tbl[] = {
|
||||||
|
|
@ -1319,6 +1333,8 @@ static const struct pci_device_id amd_ntb_pci_tbl[] = {
|
||||||
{ PCI_VDEVICE(AMD, 0x14c0), (kernel_ulong_t)&dev_data[1] },
|
{ PCI_VDEVICE(AMD, 0x14c0), (kernel_ulong_t)&dev_data[1] },
|
||||||
{ PCI_VDEVICE(AMD, 0x14c3), (kernel_ulong_t)&dev_data[1] },
|
{ PCI_VDEVICE(AMD, 0x14c3), (kernel_ulong_t)&dev_data[1] },
|
||||||
{ PCI_VDEVICE(AMD, 0x155a), (kernel_ulong_t)&dev_data[1] },
|
{ PCI_VDEVICE(AMD, 0x155a), (kernel_ulong_t)&dev_data[1] },
|
||||||
|
{ PCI_VDEVICE(AMD, 0x17d4), (kernel_ulong_t)&dev_data[1] },
|
||||||
|
{ PCI_VDEVICE(AMD, 0x17d7), (kernel_ulong_t)&dev_data[2] },
|
||||||
{ PCI_VDEVICE(HYGON, 0x145b), (kernel_ulong_t)&dev_data[0] },
|
{ PCI_VDEVICE(HYGON, 0x145b), (kernel_ulong_t)&dev_data[0] },
|
||||||
{ 0, }
|
{ 0, }
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -168,6 +168,7 @@ enum {
|
||||||
struct ntb_dev_data {
|
struct ntb_dev_data {
|
||||||
const unsigned char mw_count;
|
const unsigned char mw_count;
|
||||||
const unsigned int mw_idx;
|
const unsigned int mw_idx;
|
||||||
|
const bool is_endpoint;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct amd_ntb_dev;
|
struct amd_ntb_dev;
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue