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drm/amd/display: Add DML path for FAMS methods 

[Why]
DML needs a path for FAMS methods.

[How]
Apply instance of fams2_stream_sub_params_v2 structure with
a FAMS placeholder for DML.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Oleh Kuzhylnyi <okuzhyln@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Oleh Kuzhylnyi 2025-05-14 14:21:15 +02:00 committed by Alex Deucher
parent 35b74eccf8
commit ed8045a731
3 changed files with 16 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
View File

@ -1758,7 +1758,7 @@ static void dc_dmub_srv_ib_based_fams2_update_config(struct dc *dc,
/* copy stream static sub-state */
memcpy(&config->stream_v1[i].sub_state,
&context->bw_ctx.bw.dcn.fams2_stream_sub_params[i],
&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2[i],
sizeof(config->stream_v1[i].sub_state));
}
}

14
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
View File

@ -384,6 +384,7 @@ void dml21_build_fams2_programming(const struct dc *dc,
/* reset fams2 data */
memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES);
memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES);
memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2, 0, sizeof(union dmub_fams2_stream_static_sub_state_v2) * DML2_MAX_PLANES);
memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config));
if (dml_ctx->v21.mode_programming.programming->fams2_required) {
@ -414,9 +415,16 @@ void dml21_build_fams2_programming(const struct dc *dc,
memcpy(static_base_state,
&dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_base_params,
sizeof(union dmub_cmd_fams2_config));
memcpy(static_sub_state,
&dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_sub_params,
sizeof(union dmub_cmd_fams2_config));
if (dc->debug.fams_version.major == 3) {
memcpy(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2[num_fams2_streams],
&dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_sub_params_v2,
sizeof(union dmub_fams2_stream_static_sub_state_v2));
} else {
memcpy(static_sub_state,
&dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_sub_params,
sizeof(union dmub_cmd_fams2_config));
}
switch (dc->debug.fams_version.minor) {
case 1:

5
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -556,7 +556,10 @@ struct dcn_bw_output {
struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];
struct dmub_cmd_fams2_global_config fams2_global_config;
union dmub_cmd_fams2_config fams2_stream_base_params[DML2_MAX_PLANES];
union dmub_cmd_fams2_config fams2_stream_sub_params[DML2_MAX_PLANES];
union {
union dmub_cmd_fams2_config fams2_stream_sub_params[DML2_MAX_PLANES];
union dmub_fams2_stream_static_sub_state_v2 fams2_stream_sub_params_v2[DML2_MAX_PLANES];
};
struct dml2_display_arb_regs arb_regs;
};