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spi: dt-bindings: renesas,rzv2h-rspi: document RZ/T2H and RZ/N2H
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have four SPI peripherals. Compared to the previously supported RZ/V2H, these SoCs have a smaller FIFO, no resets, and only two clocks: PCLKSPIn and PCLK. PCLKSPIn, being the clock from which the SPI transfer clock is generated, is the equivalent of the TCLK from V2H. Document them, and use RZ/T2H as a fallback for RZ/N2H as the SPIs are entirely compatible. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251119161434.595677-11-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -9,12 +9,15 @@ title: Renesas RZ/V2H(P) Renesas Serial Peripheral Interface (RSPI)
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maintainers:
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- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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const: renesas,r9a09g057-rspi # RZ/V2H(P)
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oneOf:
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- enum:
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- renesas,r9a09g057-rspi # RZ/V2H(P)
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- renesas,r9a09g077-rspi # RZ/T2H
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- items:
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- const: renesas,r9a09g087-rspi # RZ/N2H
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- const: renesas,r9a09g077-rspi # RZ/T2H
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reg:
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maxItems: 1
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@ -36,13 +39,12 @@ properties:
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- const: tx
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clocks:
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minItems: 2
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maxItems: 3
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clock-names:
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items:
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- const: pclk
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- const: pclk_sfr
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- const: tclk
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minItems: 2
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maxItems: 3
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resets:
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maxItems: 2
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@ -62,12 +64,52 @@ required:
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- interrupt-names
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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- '#address-cells'
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- '#size-cells'
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,r9a09g057-rspi
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then:
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properties:
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clocks:
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minItems: 3
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clock-names:
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items:
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- const: pclk
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- const: pclk_sfr
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- const: tclk
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required:
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- resets
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- reset-names
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- if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,r9a09g077-rspi
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then:
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properties:
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: pclk
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- const: pclkspi
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resets: false
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reset-names: false
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unevaluatedProperties: false
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examples:
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