mirror of https://github.com/torvalds/linux.git
Merge patch series "mpi3mr: bug fixes and minor updates"
Chandrakanth Patil <chandrakanth.patil@broadcom.com> says: This series contains mpi3mr driver fixes and minor updates. Link: https://lore.kernel.org/r/20250820084138.228471-1-chandrakanth.patil@broadcom.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
commit
e5e11f666d
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@ -322,6 +322,9 @@ struct mpi3_man6_gpio_entry {
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#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01)
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#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00)
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#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01)
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#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_WARNING (0x00)
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#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_CRITICAL (0x01)
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#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_FATAL (0x02)
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#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00)
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#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01)
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#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00)
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@ -1250,6 +1253,37 @@ struct mpi3_io_unit_page17 {
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__le32 current_key[];
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};
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#define MPI3_IOUNIT17_PAGEVERSION (0x00)
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struct mpi3_io_unit_page18 {
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struct mpi3_config_page_header header;
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u8 flags;
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u8 poll_interval;
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__le16 reserved0a;
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__le32 reserved0c;
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};
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#define MPI3_IOUNIT18_PAGEVERSION (0x00)
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#define MPI3_IOUNIT18_FLAGS_DIRECTATTACHED_ENABLE (0x01)
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#define MPI3_IOUNIT18_POLLINTERVAL_DISABLE (0x00)
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#ifndef MPI3_IOUNIT19_DEVICE_MAX
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#define MPI3_IOUNIT19_DEVICE_MAX (1)
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#endif
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struct mpi3_iounit19_device {
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__le16 temperature;
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__le16 dev_handle;
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__le16 persistent_id;
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__le16 reserved06;
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};
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#define MPI3_IOUNIT19_DEVICE_TEMPERATURE_UNAVAILABLE (0x8000)
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struct mpi3_io_unit_page19 {
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struct mpi3_config_page_header header;
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__le16 num_devices;
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__le16 reserved0a;
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__le32 reserved0c;
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struct mpi3_iounit19_device device[MPI3_IOUNIT19_DEVICE_MAX];
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};
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#define MPI3_IOUNIT19_PAGEVERSION (0x00)
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struct mpi3_ioc_page0 {
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struct mpi3_config_page_header header;
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__le32 reserved08;
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@ -2356,7 +2390,9 @@ struct mpi3_device0_vd_format {
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__le16 io_throttle_group;
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__le16 io_throttle_group_low;
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__le16 io_throttle_group_high;
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__le32 reserved0c;
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u8 vd_abort_to;
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u8 vd_reset_to;
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__le16 reserved0e;
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};
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#define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00)
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#define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01)
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@ -9,9 +9,11 @@
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#define MPI3_NVME_ENCAP_CMD_MAX (1)
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#endif
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#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_MASK (0x0002)
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#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_SHIFT (1)
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#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_FAIL_ONLY (0x0000)
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#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_ALL (0x0002)
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#define MPI3_NVME_FLAGS_SUBMISSIONQ_MASK (0x0001)
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#define MPI3_NVME_FLAGS_SUBMISSIONQ_SHIFT (0)
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#define MPI3_NVME_FLAGS_SUBMISSIONQ_IO (0x0000)
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#define MPI3_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0001)
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@ -11,6 +11,7 @@
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#define MPI3_SAS_DEVICE_INFO_STP_INITIATOR (0x00000010)
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#define MPI3_SAS_DEVICE_INFO_SMP_INITIATOR (0x00000008)
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#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_MASK (0x00000007)
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#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_SHIFT (0)
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#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_NO_DEVICE (0x00000000)
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#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_END_DEVICE (0x00000001)
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#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_EXPANDER (0x00000002)
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@ -18,7 +18,7 @@ union mpi3_version_union {
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#define MPI3_VERSION_MAJOR (3)
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#define MPI3_VERSION_MINOR (0)
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#define MPI3_VERSION_UNIT (35)
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#define MPI3_VERSION_UNIT (37)
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#define MPI3_VERSION_DEV (0)
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#define MPI3_DEVHANDLE_INVALID (0xffff)
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struct mpi3_sysif_oper_queue_indexes {
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@ -56,8 +56,8 @@ extern struct list_head mrioc_list;
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extern int prot_mask;
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extern atomic64_t event_counter;
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#define MPI3MR_DRIVER_VERSION "8.14.0.5.50"
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#define MPI3MR_DRIVER_RELDATE "27-June-2025"
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#define MPI3MR_DRIVER_VERSION "8.15.0.5.50"
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#define MPI3MR_DRIVER_RELDATE "12-August-2025"
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#define MPI3MR_DRIVER_NAME "mpi3mr"
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#define MPI3MR_DRIVER_LICENSE "GPL"
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@ -697,6 +697,8 @@ struct tgt_dev_vd {
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u16 tg_id;
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u32 tg_high;
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u32 tg_low;
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u8 abort_to;
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u8 reset_to;
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struct mpi3mr_throttle_group_info *tg;
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};
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@ -738,6 +740,8 @@ enum mpi3mr_dev_state {
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* @wwid: World wide ID
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* @enclosure_logical_id: Enclosure logical identifier
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* @dev_spec: Device type specific information
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* @abort_to: Timeout for abort TM
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* @reset_to: Timeout for Target/LUN reset TM
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* @ref_count: Reference count
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* @state: device state
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*/
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@ -2353,6 +2353,8 @@ static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
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{
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int retval = 0;
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u16 num_queues = 0, i = 0, msix_count_op_q = 1;
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u32 ioc_status;
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enum mpi3mr_iocstate ioc_state;
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num_queues = min_t(int, mrioc->facts.max_op_reply_q,
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mrioc->facts.max_op_req_q);
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@ -2408,6 +2410,14 @@ static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
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retval = -1;
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goto out_failed;
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}
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ioc_status = readl(&mrioc->sysif_regs->ioc_status);
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ioc_state = mpi3mr_get_iocstate(mrioc);
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if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
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ioc_state != MRIOC_STATE_READY) {
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mpi3mr_print_fault_info(mrioc);
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retval = -1;
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goto out_failed;
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}
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mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
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ioc_info(mrioc,
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"successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
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@ -5420,6 +5430,7 @@ int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
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mpi3mr_reset_rc_name(reset_reason));
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mrioc->device_refresh_on = 0;
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scsi_block_requests(mrioc->shost);
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mrioc->reset_in_progress = 1;
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mrioc->stop_bsgs = 1;
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mrioc->prev_reset_result = -1;
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@ -5528,6 +5539,7 @@ int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
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if (!retval) {
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mrioc->diagsave_timeout = 0;
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mrioc->reset_in_progress = 0;
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scsi_unblock_requests(mrioc->shost);
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mrioc->pel_abort_requested = 0;
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if (mrioc->pel_enabled) {
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mrioc->pel_cmds.retry_count = 0;
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@ -5552,6 +5564,7 @@ int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
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mrioc->device_refresh_on = 0;
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mrioc->unrecoverable = 1;
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mrioc->reset_in_progress = 0;
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scsi_unblock_requests(mrioc->shost);
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mrioc->stop_bsgs = 0;
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retval = -1;
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mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
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@ -1308,6 +1308,12 @@ static void mpi3mr_update_tgtdev(struct mpi3mr_ioc *mrioc,
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if (vdinf->vd_state == MPI3_DEVICE0_VD_STATE_OFFLINE)
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tgtdev->is_hidden = 1;
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tgtdev->non_stl = 1;
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tgtdev->dev_spec.vd_inf.reset_to =
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max_t(u8, vdinf->vd_reset_to,
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MPI3MR_INTADMCMD_TIMEOUT);
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tgtdev->dev_spec.vd_inf.abort_to =
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max_t(u8, vdinf->vd_abort_to,
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MPI3MR_INTADMCMD_TIMEOUT);
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tgtdev->dev_spec.vd_inf.tg_id = vdinf_io_throttle_group;
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tgtdev->dev_spec.vd_inf.tg_high =
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le16_to_cpu(vdinf->io_throttle_group_high) * 2048;
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@ -2049,8 +2055,8 @@ static void mpi3mr_fwevt_bh(struct mpi3mr_ioc *mrioc,
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if (!fwevt->process_evt)
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goto evt_ack;
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dprint_event_bh(mrioc, "processing event(0x%02x) in the bottom half handler\n",
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fwevt->event_id);
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dprint_event_bh(mrioc, "processing event(0x%02x) -(0x%08x) in the bottom half handler\n",
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fwevt->event_id, fwevt->evt_ctx);
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switch (fwevt->event_id) {
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case MPI3_EVENT_DEVICE_ADDED:
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@ -2866,12 +2872,14 @@ static void mpi3mr_preparereset_evt_th(struct mpi3mr_ioc *mrioc,
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"prepare for reset event top half with rc=start\n");
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if (mrioc->prepare_for_reset)
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return;
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scsi_block_requests(mrioc->shost);
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mrioc->prepare_for_reset = 1;
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mrioc->prepare_for_reset_timeout_counter = 0;
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} else if (evtdata->reason_code == MPI3_EVENT_PREPARE_RESET_RC_ABORT) {
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dprint_event_th(mrioc,
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"prepare for reset top half with rc=abort\n");
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mrioc->prepare_for_reset = 0;
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scsi_unblock_requests(mrioc->shost);
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mrioc->prepare_for_reset_timeout_counter = 0;
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}
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if ((event_reply->msg_flags & MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK)
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@ -3076,8 +3084,8 @@ void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
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}
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if (process_evt_bh || ack_req) {
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dprint_event_th(mrioc,
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"scheduling bottom half handler for event(0x%02x),ack_required=%d\n",
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evt_type, ack_req);
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"scheduling bottom half handler for event(0x%02x) - (0x%08x), ack_required=%d\n",
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evt_type, le32_to_cpu(event_reply->event_context), ack_req);
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sz = event_reply->event_data_length * 4;
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fwevt = mpi3mr_alloc_fwevt(sz);
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if (!fwevt) {
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@ -3915,11 +3923,13 @@ int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,
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if (scsi_tgt_priv_data)
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atomic_inc(&scsi_tgt_priv_data->block_io);
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if (tgtdev && (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_PCIE)) {
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if (cmd_priv && tgtdev->dev_spec.pcie_inf.abort_to)
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timeout = tgtdev->dev_spec.pcie_inf.abort_to;
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else if (!cmd_priv && tgtdev->dev_spec.pcie_inf.reset_to)
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timeout = tgtdev->dev_spec.pcie_inf.reset_to;
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if (tgtdev) {
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if (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_PCIE)
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timeout = cmd_priv ? tgtdev->dev_spec.pcie_inf.abort_to
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: tgtdev->dev_spec.pcie_inf.reset_to;
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else if (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_VD)
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timeout = cmd_priv ? tgtdev->dev_spec.vd_inf.abort_to
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: tgtdev->dev_spec.vd_inf.reset_to;
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}
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init_completion(&drv_cmd->done);
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@ -413,11 +413,13 @@ static void mpi3mr_remove_device_by_sas_address(struct mpi3mr_ioc *mrioc,
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sas_address, hba_port);
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if (tgtdev) {
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if (!list_empty(&tgtdev->list)) {
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list_del_init(&tgtdev->list);
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was_on_tgtdev_list = 1;
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if (tgtdev->state == MPI3MR_DEV_REMOVE_HS_STARTED) {
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list_del_init(&tgtdev->list);
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mpi3mr_tgtdev_put(tgtdev);
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}
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}
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}
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spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
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if (was_on_tgtdev_list) {
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if (tgtdev->host_exposed)
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@ -2079,6 +2081,8 @@ int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle)
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link_rate = (expander_pg1.negotiated_link_rate &
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MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK) >>
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MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT;
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if (link_rate < MPI3_SAS_NEG_LINK_RATE_1_5)
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link_rate = MPI3_SAS_NEG_LINK_RATE_1_5;
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mpi3mr_update_links(mrioc, sas_address_parent,
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handle, i, link_rate, hba_port);
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}
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@ -2388,6 +2392,9 @@ int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc,
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link_rate = mpi3mr_get_sas_negotiated_logical_linkrate(mrioc, tgtdev);
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if (link_rate < MPI3_SAS_NEG_LINK_RATE_1_5)
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link_rate = MPI3_SAS_NEG_LINK_RATE_1_5;
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mpi3mr_update_links(mrioc, sas_address_parent, tgtdev->dev_handle,
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parent_phy_number, link_rate, hba_port);
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