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phy: renesas: r8a779f0-ether-serdes: add new step added to latest datasheet 

R-Car S4-8 datasheet Rev.1.20 describes some additional register
settings at the end of the initialization.

Signed-off-by: Michael Dege <michael.dege@renesas.com>
Link: https://lore.kernel.org/r/20250703-renesas-serdes-update-v4-2-1db5629cac2b@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Michael Dege 2025-07-03 13:07:24 +02:00 committed by Vinod Koul
parent d337c55758
commit e4a8db93b5
1 changed files with 28 additions and 0 deletions
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28
drivers/phy/renesas/r8a779f0-ether-serdes.c
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@ -49,6 +49,13 @@ static void r8a779f0_eth_serdes_write32(void __iomem *addr, u32 offs, u32 bank,
iowrite32(data, addr + offs);
}
static u32 r8a779f0_eth_serdes_read32(void __iomem *addr, u32 offs, u32 bank)
{
iowrite32(bank, addr + R8A779F0_ETH_SERDES_BANK_SELECT);
return ioread32(addr + offs);
}
static int
r8a779f0_eth_serdes_reg_wait(struct r8a779f0_eth_serdes_channel *channel,
u32 offs, u32 bank, u32 mask, u32 expected)
@ -319,6 +326,7 @@ static int r8a779f0_eth_serdes_hw_init_late(struct r8a779f0_eth_serdes_channel
*channel)
{
int ret;
u32 val;
ret = r8a779f0_eth_serdes_chan_setting(channel);
if (ret)
@ -332,6 +340,26 @@ static int r8a779f0_eth_serdes_hw_init_late(struct r8a779f0_eth_serdes_channel
r8a779f0_eth_serdes_write32(channel->addr, 0x03d0, 0x380, 0x0000);
val = r8a779f0_eth_serdes_read32(channel->addr, 0x00c0, 0x180);
r8a779f0_eth_serdes_write32(channel->addr, 0x00c0, 0x180, val | BIT(8));
ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0100, 0x180, BIT(0), 1);
if (ret)
return ret;
r8a779f0_eth_serdes_write32(channel->addr, 0x00c0, 0x180, val & ~BIT(8));
ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0100, 0x180, BIT(0), 0);
if (ret)
return ret;
val = r8a779f0_eth_serdes_read32(channel->addr, 0x0144, 0x180);
r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, val | BIT(4));
ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0180, 0x180, BIT(0), 1);
if (ret)
return ret;
r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, val & ~BIT(4));
ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0180, 0x180, BIT(0), 0);
if (ret)
return ret;
return r8a779f0_eth_serdes_monitor_linkup(channel);
}