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dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSE
Document support for Airoha AN8855 Switch EFUSE used to calibrate internal PHYs and store additional configuration info. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250912131415.303407-5-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/nvmem/airoha,an8855-efuse.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Airoha AN8855 Switch EFUSE
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maintainers:
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- Christian Marangi <ansuelsmth@gmail.com>
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description:
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Airoha AN8855 EFUSE used to calibrate internal PHYs and store additional
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configuration info.
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$ref: nvmem.yaml#
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properties:
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compatible:
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const: airoha,an8855-efuse
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'#nvmem-cell-cells':
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const: 0
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required:
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- compatible
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- '#nvmem-cell-cells'
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unevaluatedProperties: false
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examples:
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- |
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efuse {
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compatible = "airoha,an8855-efuse";
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#nvmem-cell-cells = <0>;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
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reg = <0xc 0x4>;
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};
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shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
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reg = <0x10 0x4>;
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};
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shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
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reg = <0x14 0x4>;
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};
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shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
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reg = <0x18 0x4>;
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};
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shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
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reg = <0x1c 0x4>;
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};
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shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
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reg = <0x20 0x4>;
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};
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shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
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reg = <0x24 0x4>;
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};
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shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
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reg = <0x28 0x4>;
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};
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shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c {
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reg = <0x2c 0x4>;
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};
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shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 {
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reg = <0x30 0x4>;
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};
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shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 {
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reg = <0x34 0x4>;
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};
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shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 {
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reg = <0x38 0x4>;
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};
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shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c {
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reg = <0x4c 0x4>;
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};
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shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 {
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reg = <0x50 0x4>;
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};
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shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 {
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reg = <0x54 0x4>;
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};
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shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 {
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reg = <0x58 0x4>;
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};
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shift_sel_port4_tx_a: shift-sel-port4-tx-a@5c {
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reg = <0x5c 0x4>;
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};
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shift_sel_port4_tx_b: shift-sel-port4-tx-b@60 {
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reg = <0x60 0x4>;
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};
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shift_sel_port4_tx_c: shift-sel-port4-tx-c@64 {
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reg = <0x64 0x4>;
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};
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shift_sel_port4_tx_d: shift-sel-port4-tx-d@68 {
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reg = <0x68 0x4>;
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};
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};
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};
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